Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Application Engineer

Pre-Sales Solution EngineeringConfirmed live in the last 24 hours

Full-timeZhubei City, TaiwanNo salary listedIn-person

About the Job

Requirements

A Master's degree and at least 3 years of work experience, or a Bachelor's degree and at least 5 years of experience in integrated circuit design.
Familiarity with the full application place-and-route flow, including logical and physical aspects such as timing, signal integrity, congestion, routing design-rule checking, hierarchical design, and multi-supply-voltage knowledge and methodology.
Familiarity with shell, Perl, and Tcl scripting languages.
Ability to communicate in English and Chinese.

Responsibilities

Provide key technical support in digital integrated-circuit design implementation product demonstrations and sales presentations.
Demonstrate hands-on ability in the full application place-and-route flow, including floorplanning, placement, timing analysis, clock-tree synthesis, signoff timing, and physical verification closure methodology.
Support key customer engagements to increase business.
Play a leading role among team members while receiving little instruction on routine and general assignments.

Desired Qualifications

Real design tape-out experience, especially for advanced-node design.
Experience with Cadence Innovus.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:
• To provide key technical support in digital IC design implementation product demonstration, and sales presentations.
• To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing and PV closure methodology.
• To support key customer engagements on the business increase.
• Have real design tape-out experience especially (nice to have) for advanced node design.
• To play a leading role among other team members, while receive little instruction on routine and general assignments

Position Requirements:
• Master better with 3+ years working experience or Bachelor better with 5+ years’ experience in IC design. (Cadence Innovus experience will be a plus)
• Familiar with full APR flow including both logical + physical related (timing, SI , congestion , routing drc , hier design ....etc .) and MSV knowledge + methodology.
• Good communication in English and Chinese, good confidence and good attitude and self-motivation .
• Be familiar with shell/perl/tcl etc. script language.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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