Eliyan

D2D/C2C interconnect IP licensing

Digital Verification Engineer - Staff +

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeNo salary listedIn-person

About the Job

Requirements

A Master's or Ph.D. in Electrical Engineering or a related field, with at least 6 years of experience.
Hands-on experience verifying serial transmission protocols and products, preferably retimer, gearbox, Ethernet PMA/PCS logic.
Strong expertise in UVM, verification environments, and assertion coding with SystemVerilog.
Proficiency with third-party tools for regression management and coverage analysis.
At least 3 years of experience working on Ethernet 802.3 standards clauses related to 100G, 200G, 400G, and 800G, Auto-Negotiation, and Link Training.
A strong focus on innovation across digital verification, including automation of routine activities and quality-improvement methods.
Experience verifying third-party mixed-signal IPs and integrating VIPs.
A proven track record working in a startup-like environment.

Responsibilities

Develop and execute verification plans for connectivity IPs and chiplets.
Create and maintain SystemVerilog/UVM-based verification environments.
Write and debug SystemVerilog/UVM-compliant test cases for block and chip levels.
Maintain a regression environment to enable design CI/CD pipelines.
Collaborate with design engineers to ensure design quality through continuous microarchitecture, test-plan, and coverage reviews.
Develop, maintain, and track test-plan items and progress toward RTL freeze.
Stay up to date with industry trends, emerging technologies, and progress in standards bodies.
Ensure IP compliance with Ethernet standards (IEEE 802.3).
Integrate third-party VIPs and coordinate feature and bug-tracking requests.
Provide technical leadership to junior verification engineers.
Create, improve, and maintain DPI-based firmware simulation environments.
Create, improve, and maintain GLS environments for functional and power simulations.

Desired Qualifications

Knowledge of DRAM controllers/PHYs and HBM memory.

Join the leading chiplet startup! As an Eliyan staff digital verification engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities:

Develop and execute verification plans for connectivity IPs and Chiplets
Create and maintain SystemVerilog/UVM-based verification environments
Write and debug SystemVerilog/UVM compliant test cases for block and chip level
Maintain a regression environment for enabling design CI/CD pipelines
Collaborate with design engineers to ensure design quality with continuous microarchitecture, test-plan, and coverage reviews
Develop, maintain, and track various test plan items and progress towards RTL freeze
Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
Ensure IP compliance with Ethernet standards (IEEE 802.3)
Integration 3rd party VIPs and coordinate feature/bug tracking requests
Perform in the capacity of a technical leader for junior verification engineers
Create, improve, maintain DPI based FW simulation environments
Create, improve, maintain GLS environments for functional and power simulations

Qualifications:

Masters or Ph.D in Electrical Engineering and related fields with 6+ years of experience
Hands on experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
Strong expertise in UVM, test environment and assertion coding with SystemVerilog
Proficiency in 3 rd party tools for regression management and coverage analysis
3+ experience working on Ethernet 802.3 standards’ clauses related to 100G, 200G, 400G, 800G; Auto-Negotiation and Link Training
Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement
Experience in verifying 3 rd party mixed signal IPs as well as integration of VIPs
Proven track record of being part of a start-up like environment

About the Company

Eliyan

D2D/C2C interconnect IP licensing

Eliyan provides high-performance interconnect IP and chiplets for chiplet-based systems, including NuLink PHY for die-to-die and chip-to-chip connections and NuGear memory/I O chips, plus a Universal Memory Interface. Its NuLink uses simultaneous bidirectional signaling on a single wire to achieve high bandwidth while staying compatible with standards like UCIe and BoW and using standard organic substrates. The company licenses its IP to chip makers rather than selling completed hardware, focusing on reducing cost, simplifying supply chains, and boosting system-level performance for data centers, AI accelerators, and HPC workloads. Eliyan aims to enable scalable, flexible multi-die designs that can connect to different memory types (HBM, GDDR, DDR) across future process nodes.

Company size: 51-200
Company stage: Series C
Total funding: $295M
Headquarters: Santa Clara, CA
Founded: 2021

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