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Cadence Design Systems

Develops EDA software, IP, verification tools

RTL2GDS IC Senior Principal Design Engineer

Full-TimeUpdated on 10/23/2026
$161k - $299k/yr+ Bonus + Equity
Expert
Bachelor's, Master's, PhD
San Jose, CA, USA
In Person
Hardware EngineeringSilicon & ASIC Design

About the job

Requirements
  • Requires a BS, MS, or PhD in Electrical Engineering, with or alternatively 10–12 years of industry-related experience in design and electronic design automation, specifically digital implementation and signoff.
  • Understand the ASIC design implementation process and its steps.
  • Have strong hands-on experience with place and route tools, including Innovus, ICC2, and Fusion Compiler.
  • Have exposure to and experience with synthesis tools, including Genus, RTL Compiler, and Design Compiler.
  • Have experience with electronic design automation tools in integrated-circuit digital implementation and signoff flows, including static timing analysis tools.
  • Have strong static timing analysis and Synopsys Design Constraints debugging abilities.
  • Have essential automation skills using Perl, Tcl, and shell scripting.
  • Have strong analytical skills covering digital implementation.
  • Have a proven track record of working in a fast-paced environment.
  • Have customer interaction and presentation skills.
Responsibilities
  • Provide technical support to customers in digital design implementation and signoff, including synthesis, place and route, design closure, and timing and power signoff.
  • Guide customers on using Cadence technologies to achieve design goals and meet project schedules.
  • Conduct technical presentations and product demonstrations.
  • Drive technical evaluations and benchmarks to successful outcomes.
  • Work closely with research and development to enhance tools and methodologies to meet and exceed customer requirements.
  • Drive adoption and proliferation of Cadence tools and technologies.
  • Amend and augment workflows as needed using Tcl or other programming skills to meet objectives and improve results.
  • Capture best practices and lessons learned from evaluations and benchmarks and use them to improve efficiency and success in future engagements.
  • Provide technical support in developing business cases for process improvement projects.
  • Provide mentorship to junior engineers.
Desired Qualifications
  • Low-power analysis experience.
  • Clock design and analysis experience.
  • Hands-on experience with 7 nm or 5 nm technology nodes.

About the company

C

Cadence Design Systems

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cbWebsite

Cadence Design Systems provides software, hardware, and IP for electronic design automation (EDA) to help customers design advanced semiconductor chips and electronic systems. Its tools cover system-level design and verification, digital and analog IC design, and custom design flows, with IP offerings like Tensilica processors and DSP cores available for licensing. It differentiates itself by offering an end-to-end EDA portfolio and deep collaboration with industry leaders across implementation, verification, and IP. The goal is to help customers bring sophisticated silicon and electronics to market faster while reducing risk and improving productivity across AI, audio, video, and automotive applications.

Company Size

10,001+

Company Stage

IPO

Headquarters

San Jose, California

Founded

1988

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Simplify's Take

What believers are saying

  • Q2 2026 revenue rose 24% to $1.584 billion, lifting full-year guidance.
  • Intel and Honda validated Cadence’s AI and IP products with fresh design wins.
  • SPDRM 2026.2.3 boosted concurrency 50%, strengthening Cadence’s enterprise workflow moat.

What critics are saying

  • Cadence sued Suzhou Tianzhun in August 2026 over cracked software and copyright infringement.
  • Cadence trades above 15 times revenue; any AI demand slowdown can compress multiples fast.
  • Synopsys’ Ansys bundle threatens Cadence’s pricing power in verification, IP, and system design.

What makes Cadence Design Systems unique

  • Cadence’s 2026 ChipStack agents automate spec-to-RTL, verification, and PPA optimization.
  • Cadence’s PCIe 6.0 subsystem passed July 2026 compliance first-pass on TSMC N3.
  • Cadence’s July 2026 backlog hit $8.1 billion, showing entrenched design-in lock-in.

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Benefits

  • Health Insurance
  • Dental Insurance
  • Life Insurance
  • Flexible Work Hours
  • Paid Vacation
  • Paid Sick Leave

Growth & Insights and Company News

6 month growth

1%

1 year growth

-1%

2 year growth

-1%
Yahoo Finance
Oct 23rd, 2026
3 resilient software stocks: JFrog, Cadence and CLEAR Secure with up to 86.8% gross margins

Software is cutting operating costs for businesses, and the industry's 54.6% return over the last six months has beaten the S&P 500 by 45.5 percentage points. Yet low barriers to entry mean fierce competition, and few companies will thrive long term. Three software stocks stand out as resilient, according to StockStory. JFrog (NASDAQ:FROG), valued at $11.58 billion, sells a platform for creating, storing, and distributing software packages. Billings growth averaged 31.5% over the last year, and its free cash flow margin is 28.3%. Shares trade at $93.19, or 16.7x forward price-to-sales. Cadence Design Systems (NASDAQ:CDNS), valued at $89.8 billion, supplies software and hardware for chip design. Its gross margin is 86.8% and billings growth averaged 17.9%. The stock trades at $308.58, or 13.4x forward price-to-sales. CLEAR Secure (NYSE:YOU), valued at $4.69 billion, offers biometric identity verification. Revenue grew 36% annually over five years, with a 50.8% free cash flow margin. Shares trade at $45.43, or 3.9x forward price-to-sales.

Yahoo Finance
Oct 20th, 2026
Cadence stock up 105.2% in five years while typical software peer fell 48.2%

Cadence Design Systems (CDNS) shares rose 105.2% in the five years to October 19, 2026, beating 119 of 125 companies in the application software industry. The typical company in that industry fell 48.2%, so the industry did not carry the stock. The S&P 500 gained 70.2% over the period. The typical information technology company fell 23.9%. Earnings per share rose 107.0%, closely tracking the share price. Revenue grew an average of 15.5% a year over three years, against 11.1% for the typical peer. Management raised its fiscal 2026 revenue growth guidance to 19%. Fiscal third-quarter results are expected on or around October 26, 2026.

Yahoo Finance
Oct 14th, 2026
Cadence stock rose 13x in a decade to $129,800, but fell 20% or more seven times

A $10,000 investment in Cadence Design Systems (CDNS) stock grew to about $129,800 over the past ten years, before dividends. The same sum in the S&P 500 reached about $36,500. Holding it was hard. The stock fell 20% or more from a closing high seven times, and three of those drops reached 30% or more. The latest fall was the deepest. Shares dropped 34% from early June to mid-September 2026, while the S&P 500 slipped 0.3%. The business held up. Twelve-month revenue rose 5.6% over that span, and operating margin stayed near 31%. The stock has since risen 22% from its September low but remains about 20% below its June high.

Yahoo Finance
Oct 2nd, 2026
Fair Isaac faces mortgage score challenge while Cadence grows across all products

Fair Isaac and Cadence Design Systems both sell products customers cannot easily replace, but their growth drivers differ significantly. Cadence's chip design software grows across all product groups, whilst Fair Isaac's growth stems primarily from raising prices on its FICO Score. In September 2026, the Federal Housing Finance Agency announced it would start using VantageScore, a cheaper rival, to set mortgage prices. This decision particularly affects Fair Isaac, whose Scores revenue grew 41% in fiscal Q3 2026, driven mainly by higher mortgage score prices. Cadence carries far less debt, at 2.7% of market value versus Fair Isaac's 40%. Fair Isaac trades at 18.4 times earnings compared to Cadence's 69.7 times. Fair Isaac's share price has fallen 56% over the past year, whilst Cadence is down 0.2%. Fair Isaac has not reported results since the government announcement.

Yahoo Finance
Oct 1st, 2026
Synopsys vs Cadence: Which chip design software giant offers better value after Ansys acquisition?

Synopsys and Cadence Design Systems dominate the chip design software market, yet both stocks have fallen over the past year despite strong semiconductor sector performance. Synopsys generated $9.42 billion in revenue, growing 42.4% last quarter largely through its Ansys acquisition. However, the deal brought significant costs: operating margin sits at 14.52%, total debt reached $10.84 billion, and return on equity fell to 3.66%. Cadence achieved 24.2% organic revenue growth to $5.84 billion without major acquisitions. It maintains a 28.58% operating margin and carries just $2.65 billion in debt. The valuation gap reflects these differences. Cadence trades at over 15 times revenue versus Synopsys's 8.5 times. On trailing earnings, Synopsys appears more expensive at 73 times versus 65 times for Cadence. Both companies benefit from customer lock-in, as switching design tools requires costly revalidation and retraining. AI chip designers have strengthened demand for both vendors. At Q2 2026, 85 hedge funds held Synopsys shares worth $4.1 billion, whilst 69 held Cadence positions valued at $3.2 billion.