Static Timing Analysis Senior Engineer - Hardware Engineering

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

·STASetup & Signoff: PerformSTAsetup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem

·Timing Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools likePrimeTime andTempus.

·Flow Optimization: RunSTAflows and correlate Spice toSTAresults.

·Methodology Development: Evaluate timing methodologies/tools across technology nodes and automateSTA/PD flows usingTCL/Perl/Python.

·Cross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.

·Low-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.

·ECO Timing Flow: Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Education:

oB.Tech/M.Tech/MS in Electrical/Electronics/Microelectronics/VLSI.

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