Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Design Engineer

Hardware EngineeringConfirmed live in the last 24 hours

Full-timeHyderabad, Telangana, IndiaNo salary listedIn-person

About the Job

Requirements

A bachelor's degree in Electrical or Electronic Engineering, or equivalent.
Four to seven years of work experience in PDK development and CAD enablement.
Expertise in Cadence Python, SKILL, and Perl programming languages.
Knowledge of deep sub-micron CMOS processes, device physics, and layout design.
Experience with the Cadence custom IC Virtuoso platform to create layout test structures, validate verification rules, and troubleshoot errors.
Experience developing PDK device library components and definitions, including SKILL parameterized cells (Pcells), symbols, CDF, callbacks, and simulation/netlisting.
Experience with physical verification tools for DRC, LVS, and parasitic extraction.

Responsibilities

Develop and integrate foundry rule decks and technology files to support PDKs, using foundry-provided process design kits as a starting point.
Develop PDK QA, verification, and release methodologies for decks and specialized setups, including track patterns to aid in layout.
Develop physical verification methodology, including installation, development, qualification, automation, and support.
Develop scripts to automate LVS, DRC, RM, IR, and parasitic extraction flows.
Support layout teams with verification flow issues.
Ensure QA of integrated PDKs with the custom design environment.
Add sub-scripts to improve efficiency in the QA process with adequate coverage.
Provide real-time support for tools, create bug workarounds, and file CCRs with R&D.
Develop rule decks by implementing process design rules into physical verification rule decks and performing QC on the rule decks.
Interface with design teams and the foundry team to develop and verify PDKs.
Develop, own, and maintain an automation framework to improve design-environment efficiency.

Desired Qualifications

Cadence PVS and Assura experience is a plus.
Working knowledge of revision control software such as Git, SOS, Subversion, or Synchronicity.
Understanding of Pcell creation and enhancements to Pcell parameters and device callbacks is a plus.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:

To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
Responsible for physical verification methodology, including installation, development, qualification, automation, and support –
- To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows.
- And to support layout teams in verification flow issues.
Ensuring QA of the integrated PDK’s with the custom design environment
- Add sub scripts to improve efficiency on QA process with adequate coverage.
General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D
Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks.
Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs.
Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment.

Position Requirements:

Bachelor’s Degree in Electrical/Electronic Engineering or equivalent .
4-7 years of Work experience in PDK development and CAD enablement.
Expertise in Cadence Python, SKILL, Perl programming languages.
Knowledge of deep sub-micron CMOS processes, device physics and layout design.
Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting.
Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus.
Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)
Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus
Excellent technical problem solving skills.
Excellent communication and presentation skills.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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