A

Apple

Designs phones, computers and their operating systems

Physical Design Engineer

Silicon & ASIC DesignPosted on Nov 5
Full-time

About the Job

Requirements

  • A master's degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field, and 2 years of experience in the job offered or a related occupation.
  • Experience and/or education using PNR tools such as ICC, ICC2, or Innovus for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for SoC partitions.
  • Experience and/or education using timing analysis tools such as Synopsys PrimeTime for timing analysis and timing ECO generation to close timing for SoC partitions.
  • Experience and/or education using TCL, Perl, or Python and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts to aid partition closure.
  • Understanding of physical design construction and analysis flows and methodologies to execute, close, and sign off SoC partitions.
  • Understanding of transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure, and signoff of SoC partitions.
  • Understanding of results from EMIR analysis tools such as Voltus or RedHawk, and generating fixes to address violations or improve quality of results.
  • Understanding of results from physical verification tools such as Calibre, and generating fixes to address violations.
  • Understanding of results from LEC and low-power verification tools such as Conformal, Formality, VCLP, and CLP, and making fixes to address violations.

Responsibilities

  • Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
  • Complete netlist-to-GDS2 implementation for partitions to meet schedule and design goals.
  • Own timing, physical, and electrical verification, and drive signoff closure for partitions.
  • Resolve physical design and flow issues by identifying potential solutions and driving execution.
  • Serve as a focal point for place and route, driving work among place-and-route engineers, setting goals and milestones, planning short- and long-term work, and understanding dependencies across top-level design, static timing analysis, block place and route, and other domains.
  • Work with the physical design team to drive methodologies and best-known methods, streamline physical design work, develop guidelines and checklists, drive execution, and track progress.
  • Drive timing closure through physical synthesis and place-and-route tools, working with ASIC vendors.
  • Drive front-end and back-end implementation from RTL to GDS2, including synthesis, formal verification, floor planning, net listing, timing constraints, timing and power convergence, and ECO implementation.
  • Perform hands-on physical implementation and timing closure of core platforms and SoCs.
  • Streamline timing signoff criteria, timing analysis methodologies, and flows, and develop or enhance ECO generation scripts for timing closure.
  • Own floor planning, physical synthesis, and physical design closure of large, complex designs at 1 GHz or higher clock cycles.
  • Drive physical design and timing convergence for high-frequency, low-power designs at block, cluster, and/or full-chip level.

About the Company

Apple

Designs phones, computers and their operating systems

Apple designs and sells consumer electronics, from iPhone smartphones and Mac computers to tablets and wearable devices. Its operating systems manage apps and built-in functions for communication and work, while iCloud stores files and synchronizes data across devices. Customers buy additional digital services through subscriptions such as Apple Music and Apple TV, and developers distribute software through the App Store. Apple earns money from hardware sales, subscriptions and digital transactions, selling directly to customers and through retailers and mobile carriers around the world. It was founded in 1976 and has its headquarters in Cupertino, California.

Company size
10,001+
Company stage
IPO
Headquarters
Cupertino, CA
Founded
1976

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