Lead Software Engineer
Cadence Design Systems
Lead Software Engineer
Cadence Design Systems
Develops EDA software, IP, verification tools
## About the role
We build the finite-element engine behind our electrothermal and thermomechanical simulation products — the solver that our customers use to predict temperature, warpage, and stress in advanced packages, 3D-IC stacks, and PCBs. It is a large, production C++ codebase that meshes real industrial geometry with hundreds of millions of degrees of freedom and solves it in parallel.
You will join as a R&D engineer working directly with the team of simulation developers. This is a hands-on numerical-methods role: you will own features end to end — formulation on paper, implementation in C++, verification against analytical or reference solutions, and performance work on real customer cases.
## Responsibilities
- Derive, implement, and verify finite-element formulations in production C++.
- Write unit and regression tests, including verification against analytical
solutions and benchmark problems; treat a feature as unfinished until it is tested.
- Profile and optimize solver and meshing code for large models — both runtime and memory.
- Debug numerical issues on real customer cases: non-convergence, mesh quality, ill-conditioning, and accuracy loss.
- Write up formulations, assumptions, and validation results clearly enough that a colleague can reproduce them.
- Work with application engineers, QA, and product management to get features into customers' hands, and respond to what comes back.
## Required qualifications
- **PhD in Mechanical / Civil / Aerospace Engineering, Computational Mechanics,
Applied Mathematics, or a related field** (new graduates welcome), **or an MS in a
related field with 2+ years of relevant industry or research experience.**
- Solid grounding in **continuum mechanics and the finite element method**: weak
forms, isoparametric elements, numerical integration, assembly, and the
Newton–Raphson method for nonlinear problems.
- Working knowledge of **heat transfer and/or thermomechanical stress analysis** —
thermal eigenstrain, CTE mismatch, and the behaviour of layered structures.
- **Strong C++ (C++11 or later)**: you can read and safely extend a large existing
codebase, not just write greenfield code. Comfortable with pointers, memory
ownership, templates, and a debugger.
- Familiarity with **sparse linear algebra** and at least one sparse solver or
library.
- Ability to validate your own work: you reach for an analytical solution, a refined
mesh, or a patch test before you claim something is correct.
- Clear written and spoken English, and a genuine willingness to work as part of a
team — asking for review, giving it, and sharing what you learn.
## Preferred qualifications
- Experience with a commercial or open-source FEA code (Abaqus, ANSYS, LS-DYNA,
COMSOL, Code_Aster, FEniCS, deal.II, MOOSE) — as a developer, not only a user.
- Nonlinear FEA: large deformation, contact, plasticity, creep, or viscoplasticity.
- Parallel programming: OpenMP, MPI, or multithreaded C++.
- Direct and iterative sparse solvers (MUMPS, PARDISO, SuperLU, hypre/BoomerAMG,
PETSc) and graph partitioning (METIS/ParMETIS).
- Mesh generation, mesh quality metrics, or computational geometry.
- Semiconductor packaging or PCB background: 3D-IC, HBM stacks, solder reliability,
warpage.
- Development on Windows, and on Linux; Git or Perforce.
Develops EDA software, IP, verification tools
Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.
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