Senior Staff Clock Architecture Engineer - AI Hardware

Job Description

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. 

Our AI Hardware engineering team is building server-class SoCs that demand world-class clocking architecture. As a Sr. Staff Clock Architecture Engineer, you will own the complete clock strategy for the chip — from PLL selection and reference clock planning through topology, jitter budgeting, and RTL integration. This is a foundational role where your decisions shape the performance, reliability, and testability of every block on the die. 

Job Responsibilities

• Own full-chip clock architecture for server-class SoCs — define clock domains, topologies, and distribution strategy from concept through tapeout 
• Select and configure PLLs for each clock domain — evaluate PLL type, frequency plan, lock time, and noise characteristics against system requirements 
• Define reference clock architecture — plan RefClk sources, distribution paths, and isolation strategies across the SoC 
• Architect clock topologies — evaluate and implement tree, mesh, and hybrid clock networks to meet skew, latency, and power targets 
• Perform jitter simulation and analysis — model phase noise, cycle-to-cycle jitter, and accumulated jitter; validate against system timing budgets 
• Integrate PLLs into RTL — develop wrapper logic, calibration controls, frequency programming interfaces, and safe clock-switching sequences 
• Define and implement OCC (On-Chip Clock Controller) insertion strategy for DFT — ensure full scan coverage without compromising functional clock integrity 
• Own DFT clock flow — plan and validate clock gating, scan clocking, and ATPG compatibility across all clock domains 
• Define clock gating strategy for power management — align with DVFS and low-power architecture requirements 
• Architect cross-die clocking for 3D IC designs — address synchronization, latency matching, and jitter transfer across hybrid bonded die stacks 

Job Requirements

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience 
• 12+ years of clock architecture experience with full ownership of server-class SoC clock design 
• Deep expertise in PLL architecture, selection criteria, and system-level integration 
• Mastery of clock topologies — mesh, tree, and hybrid — and their PPA and SI tradeoffs 
• Hands-on jitter simulation experience — phase noise modeling, jitter budget allocation, and validation 
• Strong RTL integration experience — PLL wrappers, clock control logic, and frequency management 
• Proven expertise in OCC insertion and DFT clock flows for complex multi-domain SoCs 
• Experience with reference clock planning and cross-domain clock synchronization 
• Ability to use agentic AI flows to scale clock architecture analysis and validation