A

Axiado

AI-driven hardware security solutions for infrastructure

Senior IC Packaging Engineer

Board & Electronics DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USANo salary listedIn-person

About the Job

Requirements

  • A BSEE or MSEE in Electrical Engineering or a related field is required; a PhD is a plus.
  • At least 10 years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products.
  • Deep hands-on expertise in Flip-Chip BGA (FCBGA), System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe).
  • Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs; advanced packaging materials and substrate technologies; Design-for-Manufacturing (DFM); and yield optimization.
  • Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production.
  • Experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5/LPDDR5X, USB 3.x, or 10G interfaces.
  • Experience defining die-to-die and chiplet-based RDL/bump architecture.
  • Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
  • Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams.
  • Understanding of cost, yield, schedule, and risk trade-offs at product and portfolio levels.
  • Ability to operate autonomously, make high-impact decisions, and execute in a startup environment.

Responsibilities

  • Serve as technical authority for IC and SiP packaging across multiple products and programs.
  • Own package architecture and the technology roadmap, aligned with product, cost, and scalability goals.
  • Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
  • Perform and guide hands-on package design and physical layout, including critical structures for high-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and other multi-gigabit interfaces.
  • Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
  • Drive signal integrity/power integrity (SI/PI), thermal, mechanical, and reliability trade-offs at system and package levels.
  • Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
  • Influence product roadmap, risk management, and investment decisions through technical insight.
  • Establish scalable design methodologies, best practices, and reusable packaging flows.

Desired Qualifications

  • Cadence Allegro Package Designer (APD) or equivalent EDA tools.
  • Strong background in flip-chip BGA package design and layout.
  • SI/PI expertise, including S-parameter extraction and power distribution network (PDN) optimization using HFSS, SIwave, or Ansys Designer.
  • Experience building new packaging methodologies or platforms from scratch.

About the Company

Axiado

AI-driven hardware security solutions for infrastructure

Axiado provides AI-driven hardware security solutions that protect digital infrastructure by embedding security into servers, 5G networks, and data centers. Its core offerings—the Secure Vault core and Secure AI preemptive threat detection engine—are built into Trusted Control Units (TCUs) and deliver real-time, proactive AI-based threat detection. The TCUs are Open Compute Project (OCP) compliant, enabling faster adoption across cloud datacenters, 5G base stations, switches, and power controllers. Unlike software-only defenses, Axiado combines hardware security modules with software to meet the needs of enterprises requiring high assurance. The goal is to make data security the default across the infrastructure chain and reduce the global economic impact of cybercrime.

Company size
51-200
Company stage
Series C
Total funding
$205M
Headquarters
San Jose, CA
Founded
2017

Recently Posted Jobs

Explore more opportunities at Axiado

See more jobs