Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Design Engineer

Hardware Validation & Testing +1Confirmed live in the last 24 hours

Full-timeNo salary listedIn-person

About the Job

Requirements

At least 4 years of design or design verification experience.
Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of digital design and/or design verification fundamentals.
Experience working as part of a team or guiding and mentoring junior engineers.
Excellent knowledge of computer architecture, microarchitecture, and design verification fundamentals.
Expertise with Verilog, popular electronic design automation simulation tools, SystemVerilog assertions, and functional coverage.
Working knowledge of scripting languages such as Python, Perl, Tcl, Unix shell, or similar languages.
Knowledge of technical safety concepts and requirement specifications according to ISO 26262.
Proficiency in C and assembly language.
Excellent written and oral communication skills.
Exposure to debugging netlist or gate-level simulation.
General understanding of embedded software.

Responsibilities

For the logic design role, perform RTL implementation of Xtensa microprocessor cores, multiprocessor subsystems, and peripherals.
Implement microarchitecture in Verilog RTL, simulate and debug functionality, and run synthesis, place-and-route, and other electronic design automation scripts to meet timing, area, and power goals.
Assist with developing test plans, writing functional diagnostics, debugging failures, and analyzing coverage information for logic design.
Work closely with design verification and electronic design automation teams.
For the design verification role, verify Xtensa microprocessor cores, multiprocessor subsystems, and peripherals.
Assist with developing test plans, writing functional assembly diagnostics and UVM/SVA monitors, debugging failures, and analyzing coverage information for design verification.
Work closely with RTL design and electronic design automation teams.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Tensilica CPU/DSP Processor Team is hiring senior engineers to join our R&D teams in Pune, Bangalore and Noida. This is an amazing opportunity to work in an impactful job at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great Processor team where you can make an impact that is visible.

Lead Engineer positions are for one of the two roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Required Skills and Experience:

4+ years of Design or Design Verification experience
BS/MS in EE/Computer Engineering or a similar major.
Deep understanding of Digital Design and/or Design Verification fundamentals
Experience in working as part of a team, or guiding/mentoring junior engineers
Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
Good working knowledge of scripting languages like Python, Perl, Tcl, Unix shell or similar languages
Knowledge of technical safety concepts and requirement specifications according to ISO 26262
Proficient with C language and assembly language
Excellent written and oral communication skills necessary
Exposure to debugging netlist/gate level simulation.
General understanding of embedded SW.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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