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OpenLight and Tower Semiconductor expand PH18DA photonics ecosystem to accelerate photonic IC development. OpenLight's PDK is now available on Cadence's EDA tools, enabling PIC development on Tower's PH18DA InP-on-silicon photonics platform SANTA BARBARA, Calif., and MIGDAL HAEMEK, Israel, - August 11, 2026 - OpenLight, a leader in heterogeneous III-V-on-silicon photonic integration and custom Photonic Application-Specific Integrated Circuits (PASICs), and Tower Semiconductor (NASDAQ/TASE: TSEM), the leading foundry for high-value analog semiconductor solutions, today announced the availability of OpenLight's photonic Process Design Kit (PDK) for Tower Semiconductor's PH18DA indium phosphide (InP)-on-silicon photonics platform in Cadence's electronic design automation (EDA) tools. Developed through close technical collaboration between the companies, the PDK now enables customers to design advanced photonic integrated circuits (PICs) within a widely adopted IC design environment and accelerate development toward production. The PH18DA ecosystem brings together OpenLight's photonics IP, Tower's process and manufacturing expertise, and Cadence's leading EDA tools, enabling a streamlined path for developing advanced photonic ICs while bringing photonics design closer to established electronic IC workflows and manufacturing. "By making our PDK available on Cadence tools, we enable customers to design photonic integrated circuits within the same environment they rely on for advanced IC development," said Dr. Adam Carter, CEO at OpenLight. "This integration simplifies adoption and strengthens the path from design to production on the PH18DA platform." Designs created using OpenLight's PDK support fabrication on Tower's PH18DA InP-on-silicon photonics platform, which enables the integration of active photonic components - including lasers, modulators, and amplifiers - into a single monolithic PIC. The platform supports advanced optical systems for applications such as optical interconnects, AI infrastructure, and sensing. "In collaboration with Cadence and OpenLight, we are advancing design capabilities on the PH18DA platform through a new capability that integrates expertise across technology, IP, and EDA," said Dr. Samir Chaudhry, Vice President of Customer Design Enablement and Reliability at Tower Semiconductor. "This approach enables customers to streamline development of 400G and 1.6T laser-integrated photonic integrated circuits, while achieving co-optimized PIC and EIC designs for improved performance, power efficiency, and scalability necessary for next-generation near- and co-packaged optics (NPO/CPO) solutions." "Adding the OpenLight PDK PH18DA manufactured by Tower Semiconductor to the rich portfolio of photonics processes supported by the Cadence Photonics ecosystem is a key milestone because it marks the introduction of integrated active devices for high-performance, co-optimized electro-optical designs," said Gilles Lamant, Distinguished Engineer, Cadence. For additional information about Tower Semiconductor's SiPho technology platform, visit here. For additional information about OpenLight, visit here. About OpenLight OpenLight is a leader in the heterogeneous integration of III-V devices in silicon photonics. OpenLight's world-leading PASIC technology, supported by its process design kit (PDK), integrates all active and passive components of silicon photonics devices into a single chip, enabling high-performance, energy-efficient photonics solutions across datacom, telecom, automotive, AI, and quantum computing applications and markets. The company's recent $50 million Series A-1 funding round, bringing total funding to $84 million, reflects growing commercial momentum and accelerating customer adoption across next-generation photonics applications. The company is headquartered in Santa Barbara, California, with offices in Silicon Valley. Read more at www.openlightphotonics.com. About Tower Semiconductor Tower Semiconductor Ltd. (NASDAQ/TASE: TSEM), the leading foundry of high-value analog semiconductor solutions, provides technology, development, and process platforms for its customers in growing markets such as consumer, industrial, automotive, mobile, infrastructure, medical and aerospace and defense. Tower Semiconductor focuses on creating a positive and sustainable impact on the world through long-term partnerships and its advanced and innovative analog technology offering, comprised of a broad range of customizable process platforms such as SiPho, SiGe, BiCMOS, mixed-signal/CMOS, RF CMOS, CMOS image sensor, non-imaging sensors, displays, integrated power management (BCD and 700V), and MEMS. Tower Semiconductor also provides world-class design enablement for a quick and accurate design cycle as well as process transfer services including development, transfer, and optimization, to IDMs and fabless companies. To provide multi-fab sourcing and extended capacity for its customers, Tower Semiconductor currently owns one operating facility in Israel (200mm), two in the U.S. (200mm), and two in Japan (200mm and 300mm) which it owns through its 51% holdings in TPSCo and shares a 300mm facility in Agrate, Italy with STMicroelectronics. For more information, please visit: www.towersemi.com. Safe Harbor Regarding Forward-Looking Statements This press release includes forward-looking statements, which are subject to risks and uncertainties. Actual results may vary from those projected or implied by such forward-looking statements. A complete discussion of risks and uncertainties that may affect the accuracy of forward-looking statements included in this press release or which may otherwise affect Tower's business is included under the heading "Risk Factors" in Tower's most recent filings on Forms 20-F, F-3, F-4 and 6-K, as were filed with the Securities and Exchange Commission (the "SEC") and the Israel Securities Authority. Tower does not intend to update, and expressly disclaim any obligation to update, the information contained in this release. ### Tower Semiconductor Company Contact: Orit Shahar | +972-74-7377440 | [email protected] Tower Semiconductor Investor Relations Contact: Liat Avraham | +972-4-6506154 | [email protected]

DAC 2026 wrap-up: AI-Powered Engineering moves from vision to workflow reality. August 10, 2026 Every year, Design Automation Conference (DAC) brings big announcements, packed demos, and deep technical conversations - and this year at DAC 2026, the inflection point was AI moving from point-task assistance to workflow-level autonomy. Across a week of high-energy booth demonstrations, engaging sessions, and conversations with customers, partners, researchers, and innovators, Cadence showed how AI-driven design, accelerated compute, hardware-assisted verification, and system-level analysis are coming together to help engineering teams move from growing complexity to greater speed, precision, and confidence, reinforcing the strength of Cadence's Design for AI and AI for Design strategy. One standout moment at DAC was the excitement around AI-powered engineering. Kartik Hegde, senior software engineering group director at Cadence, and Da Yang, senior director of product, semiconductor, and EDA at NVIDIA, drew a huge audience at the DAC pavilion for their discussion on large language models (LLMs) in production chip design. A key takeaway from the session was the importance of deeply grounding AI agents in EDA tools and workflows. While generative AI has already shown its value in helping engineers write code, agentic AI points to a more transformative future in which systems can take ownership of engineering tasks, evaluate results, determine next steps, and continuously drive workflows toward closure. Cadence-NVIDIA Collaboration Showcases AI-Powered Engineering At DAC, NVIDIA highlighted its expanding collaboration with Cadence through demonstrations spanning AI-driven chip design, multiphysics simulation, and engineering automation. Featured technologies included the ChipStack AI Super Agent, Celsius Studio Platform for AI-enabled multiphysics design, and the latest ViraStack AI Super Agent, which extends agentic AI across semiconductor design workflows. Cadence also showcased CUDA-X library adoption and GPU acceleration of Cadence solutions, enabling faster simulation and AI-assisted design. The ChipStack AI Super Agent is built on NVIDIA Nemotron models and secured by the NVIDIA OpenShell runtime. At the Cadence booth, attendees also saw live demonstrations of the ChipStack, ViraStack, InnoStack, and AuraStack AI Super Agents, illustrating how specialized AI agents can streamline tasks across chip design, verification, custom and analog design, digital implementation and signoff, and PCB and advanced packaging design. Millennium Solution Stacks Take the Spotlight at DAC DAC also served as an excellent platform for Cadence to showcase the Millennium Solution Stack as a purpose-built design acceleration solution for modern EDA, multiphysics, and system analysis workloads. The message was clear: While deploying GPUs is straightforward, building a production-ready engineering environment requires an optimized combination of compute, memory, software, workflows, licensing, and support. The Millennium platform brings these elements together in a validated, enterprise-ready platform. Domain-specific Millennium solution stacks further tailor this approach with optimized GPU and CPU infrastructure, high-performance interconnects, middleware, GPU-accelerated Cadence solvers, and agentic AI for targeted applications across semiconductor design, 3D-IC signoff, multiphysics simulation, digital twins, data center design, turbomachinery, combustion, hypersonics, and other high-performance engineering domains. To unlock the full potential of the Millennium platform, Cadence is optimizing EDA and SDA solutions to take full advantage of NVIDIA accelerated computing. The Millennium M2000 Supercomputer integrates NVIDIA Blackwell systems and CUDA-X libraries, while Cadence solutions also use NVIDIA Grace CPUs and tools, including Jasper Formal Verification, are being optimized for NVIDIA Vera CPUs.The image below provides a clear view of solution readiness alongside the performance impact demonstrated through NVIDIA GPU benchmarks. The Millennium Solution Stack is positioned around three core advantages: optimized performance, faster deployment, and solution-level value. By integrating hardware, software, and AI into a single platform, the Millennium platform reduces deployment complexity, accelerates time to productivity, and enables engineers to tackle larger, more complex design and simulation workloads with greater efficiency. Hardware-Assisted Verification and Software-Driven Validation Remain Essential Another clear takeaway from DAC was that software-driven verification is a necessity for teams building today's most complex SoCs. At the Cadence booth, the combination of Palladium emulation and Protium prototyping platforms demonstrated how seamless hardware-software co-design can accelerate pre-silicon bring-up and enable teams to validate complex workloads earlier in the development cycle. These demonstrations were supported by deep technical engagement from the Cadence applications engineering team, including Hemanth Kumar Peddi and Mariana Ferreira Marques, who helped drive workload-centric conversations with attendees. Their expertise reinforced a central DAC theme: Advanced platforms are most effective when paired with practical engineering guidance, production insight, and a clear understanding of customer use cases. Celebrating Technical Leadership and the Next Generation of Innovators The conference offered an opportunity to celebrate the people advancing the design automation community. During the event, the IEEE CEDA President and DAC Chair recognized the newly elected IEEE Fellows in design automation. Cadence was proud to celebrate William Hung, corporate VP of research and development for HSV software development, as one of the newly elected IEEE Fellows, a meaningful recognition of technical excellence and sustained contributions to the field. The DAC Young Fellows Program was another highlight, marking a historic year with 241 fellows from 20 countries. Cadence had the honor of presenting during the opening ceremony, where David Junkin, academic network program manager, spoke about the future of the industry. Cadence team members also served as judges for the video contest, in which nearly 200 fellows submitted videos about their favorite DAC presentation, and 18 were recognized for their compelling submissions. The program concluded with more than 240 fellows receiving certificates, reinforcing Cadence's commitment to partnering with academia, advancing technology, and helping foster the future engineering workforce. Continuing the Momentum Beyond DAC DAC 2026 highlighted how the semiconductor industry is advancing toward faster, more intelligent engineering workflows. Throughout the event, Cadence showcased innovations spanning design, verification, simulation, and system analysis, powered by accelerated computing and physics-based technologies. From AI super agents and production-proven EDA and SDA solutions to the Millennium Solution Stacks, the portfolio demonstrated how Cadence is helping engineering teams tackle growing design complexity with greater speed, efficiency, and confidence. Thank you to everyone who visited the Cadence booth, joined its sessions, explored its demos, and shared valuable conversations throughout the week. Chip Estimate Corporation look forward to building on this momentum with customers, partners, researchers, and the broader design automation community as Chip Estimate Corporation shape the next era of intelligent, accelerated engineering. Ready to accelerate your most complex engineering workloads? Explore the Cadence Millennium Solution Stack and connect with an expert today.