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Cadence Design Systems

Develops EDA software, IP, verification tools

Design Engineering Director

Engineering LeadershipPosted on Nov 11
Full-timeAustin, TX, USANo salary listedIn-person

About the Job

Requirements

  • At least 10 years of front-end design and/or verification experience.
  • A BS or MS in Engineering or Computer Science.
  • Proven experience leading and managing complex engineering projects.
  • Extensive experience in IP creation and/or SoC and IP integration involving CPU, memory, or interfaces.
  • Expertise in RTL design using Verilog and in simulators and debuggers.
  • Hands-on experience with synthesis and SDC creation, and supporting physical design and static timing analysis teams.
  • Experience driving results in a multidisciplinary organization.

Responsibilities

  • Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
  • Define and develop microarchitectural features for IPs and subsystems to meet PPA goals.
  • Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
  • Oversee pre-silicon verification activities, including lint, clock domain crossing, formal verification, and other quality checks.
  • Work closely with design verification, physical design, architecture, and firmware engineers to ensure successful delivery.

Desired Qualifications

  • Experience with the Cadence front-end toolset.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size
10,001+
Company stage
IPO
Headquarters
San Jose, CA
Founded
1988

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