K

Kandou AI

Provides chip-to-chip AI connectivity solutions

DFT Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeNo salary listed

About the Job

Requirements

  • At least 5 years of design-for-test (DFT) experience, including implementation, test pattern development, and simulation.
  • Proven experience contributing to DFT solutions for complex designs.
  • Experience with IJTAG methodologies.
  • Experience with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
  • Experience generating ATPG patterns for different fault models, analyzing fault coverage, and converging to high coverage metrics.
  • Good debugging capability when simulating patterns with timing.
  • Experience with industry-standard electronic design automation (EDA) tools for DFT, timing, and simulation.
  • Knowledge of SystemVerilog.
  • Bachelor of Engineering in Electronics and Electrical Engineering or Computer Engineering, or equivalent or higher.
  • Good scripting skills to develop automation.
  • Excellent debugging skills.
  • Excellent communication skills and ability to work as part of a team.

Responsibilities

  • Perform hierarchical MBIST and scan insertion, and BSD implementation.
  • Generate ATPG patterns, analyze coverage, and converge to high coverage metrics.
  • Simulate patterns with timing.
  • Define test mode timing constraints, analyze timing reports, and converge timing.
  • Develop cycle-accurate functional patterns using IJTAG methodology.
  • Work closely with test and production engineering teams to debug and bring up devices at probe and final test.
  • Debug silicon issues.

About the Company

Kandou AI

Provides chip-to-chip AI connectivity solutions

Kandou AI designs and sells semiconductor connectivity hardware for AI workloads. It provides a memory fabric and CXL controllers that link processors to memory, enabling scalable, energy-efficient AI inference and training clusters built from affordable hardware. Using Copper MIMO interconnect, it reduces energy per bit and supports features like offloading AI training collectives, switchless memory for in-memory databases, and field-repairable co-packaged optics for better cooling. By targeting the data-movement bottleneck between processors and memory and offering chiplet-based fabrics and IP licensing, Kandou AI aims to make scalable AI infrastructure more accessible to hyperscalers, data centers, and system integrators.

Company size
201-500
Company stage
Late Stage VC
Total funding
$504.7M
Headquarters
Lausanne, Switzerland
Founded
2011

Recently Posted Jobs

Explore more opportunities at Kandou AI

See more jobs