ASIC Power Engineer

Summary

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams. In this highly visible role, you will be at the center of low power architecture, power modeling and correlation efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?

Minimum Qualifications

Minimum requirement of a bachelors degree. ASIC power knowledge. Experience with Power tools, e.g. PTPX and Power Artist. Understand ASIC logic design. Knowledge of low power design and UPF. Proficiency in scripting languages (Shell, Perl or Python). Basic knowledge on common SOC components, e.g. CPU, fabric, peripherals and PCIe. Strong problem solving and analytical skills.

Preferred Qualifications

Pre-silicon power estimation. Pre-silicon Power modeling. Wireless knowledge, including WIFI, BT and UWB. System architecture experience. Post-silicon power correlation experience.

Description

In this highly visible role, you will be at the center of low-power architecture, power modeling and correlation efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. In this role, you are going to work on power modeling, analysis and silicon validation tasks for wireless communication SoC Will you join us and do the best work of your life here?

Responsibilities

Define power efficient SOC architecture and schemes, write power spec. Estimate pre-silicon power. Build wireless application and atomic power model with high accuracy. Define and generate power vectors with Design and DV support. Collect pre-silicon power data using power flow and tools. Analyze and identify power reductions. Support post-silicon power correlation.