Low Power Design Engineer

Summary

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams. In this highly visible role, you will be at the center of low power logic design efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience Proven track record in power / clock / reset management logic design. Proficiency in Verilog language. Power management logic verification and debug experience. Understand ASIC low power design techniques Knowledge of CDC, RDC, STA and UPF. Proficiency in scripting languages (Shell, Perl or Python).  Knowledge and experience on common SOC components, e.g. CPU, fabric, peripherals. Strong problem solving and analytical skills.

Preferred Qualifications

SoC level power management logic experience. SOC top level integration experience. System architecture knowledge. Post-silicon functional debug and power correlation experience.

Description

In this role, you will be responsible for designing power management logic for complex wireless communication SoCs. Will you join us and do the best work of your life here?

Responsibilities

Define SoC power management features to meet product requirements. Implement power management logic. Work with XF teams to verify power management logic. Support Power team on power analysis and post-silicon correlation efforts. Post silicon bring up and debug support.