Design Engineer 2
Cadence Design Systems
Design Engineer 2
Cadence Design Systems
Develops EDA software, IP, verification tools
Minimum Qualifications:
2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications:
Experience managing small teams (at least 2 members and above)
Experience leading the complete post silicon validation efforts for at least one full project
1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
Experience conducting hiring interviews and mentoring new hires
BE/BTech/ME/MTech or equivalent
Develops EDA software, IP, verification tools
Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.
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