BEOL Process Integration Engineer - ASICS Engineering

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication, AI, and data processing transformation to help create a smarter, connected future for all.

As a Back-End Process Integration Engineer, you will play a critical role in developing and enabling advanced semiconductor technologies that drive Qualcomm's industry-leading products. You will lead process integration strategy, technology development, qualification, and manufacturing enablement across cutting-edge technology nodes, working closely with foundry partners, OSATs, design, product engineering, reliability, and manufacturing teams. Your contributions will directly impact product performance, power efficiency, quality, reliability, and yield for next-generation SoCs and heterogeneous integration solutions. 

The Back-End (BE) Process Integration team is responsible for defining, developing, and optimizing advanced interconnect technologies in collaboration with leading semiconductor foundries. Operating at the intersection of technology innovation and product execution, the team drives BEOL integration strategy for Qualcomm's most advanced mobile, computing, AI, and heterogeneous integration programs.

This role offers the opportunity to influence technology roadmaps, solve complex cross-functional integration challenges, and enable volume manufacturing of industry-leading semiconductor products spanning advanced logic, packaging, and 3D integration technologies.

Key Responsibilities:

• Lead BEOL process integration strategy and technology development for advanced nodes (2nm and beyond) in partnership with leading foundries.
• Serve as Qualcomm’s primary technical interface for BEOL process definition, optimization, qualification, and manufacturing readiness.
• Drive pathfinding and qualification of advanced packaging technologies, including 2.5D/3DIC, chiplets, and heterogeneous integration.
• Translate product PPAC (Power, Performance, Area, and Cost) requirements into robust process specifications and integration solutions.
• Optimize interconnect RC performance and evaluate process options to achieve product and technology objectives.
• Investigate yield, reliability, and parametric issues, driving root-cause analysis and corrective actions with foundry partners.
• Define process control and monitoring strategies to ensure process capability, quality, and manufacturing excellence.
• Partner with foundries on design rules, PDKs, and technology deliverables to enable successful product implementation.
• Lead technology qualification, HVM readiness, and new technology introduction (NTI) activities.
• Collaborate across design, product engineering, advanced packaging, reliability, and manufacturing teams.

Minimum Qualifications:

• B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related field.
• Advanced degree (M.S./Ph.D.) preferred for Staff and Senior Staff levels.
• 5+ years of semiconductor industry experience in Back-End Process Integration, Technology Development

Preferred Qualifications:

• Strong background in BEOL process integration for advanced logic nodes (sub-5nm preferred); experience in a fabless semiconductor company or as a foundry process engineer with strong customer-facing exposure strongly preferred.

• Deep understanding of interconnect materials and processes: Cu/Ru metallization, low-k and ultra-low-k dielectrics, barrier/liner films, and dual-damascene integration.

• Strong understanding of process interactions, yield learning, defect mechanisms, reliability, and root cause analysis.

• Experience with lithography, etch, CMP, CVD/ALD deposition, and wet clean unit processes and their interactions in an integrated flow.
• Proficiency in statistical process control and analysis tools: SPC, DOE, FMEA, Cpk/Ppk, JMP, or equivalent.

• Familiarity with electrical characterization, reliability qualification, and silicon debug.

• Strong understanding of interconnect reliability physics: electromigration, stress migration, TDDB, and time-dependent via degradation.
• Demonstrated experience interfacing with external foundry partners (TSMC, Samsung, or equivalent) on process development, design rule negotiation, and PDK/technology file deliverables from the customer side.
• Experience with failure analysis techniques (TEM, SEM, EDX, FIB) for root cause identification (a plus).
• Familiarity with heterogeneous integration processes such as hybrid bonding, wafer bonding, TSV, and backside metallization (a plus).

Keywords:

BEOL Process Integration, Interconnect, RC Optimization, Foundry Interface, PDK, DTCO, 3DIC, Heterogeneous Integration, Yield Enhancement, Technology Development

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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