Cadence Design Systems

Develops EDA software, IP, verification tools

Custom Layout Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeShanghai, ChinaNo salary listedIn-person

About the Job

Requirements

A Bachelor of Science in Electrical Engineering degree and at least 2 years of applicable experience in analog or custom layout of advanced technology nodes are required.
Proficiency with layout editing and verification tools such as Virtuoso XL and Pegasus/Calibre DRC/LVS is required.
Proficiency with EMIR tools such as Voltus-FI is required.
Hands-on experience conducting DRC/LVS/ERC analysis and EMIR analysis, and recommending appropriate solutions, is required.
A fundamental understanding of integrated circuit design technology and process/methodology is required.
Good communication skills in English are required.

Responsibilities

Perform custom layout floorplanning, create matching guides, place resistors and capacitors, reduce coupling and noise, and route sensitive signals and mixed signals.
Perform custom layout top-level hierarchy floorplanning for blocks and power.
Work on high-speed mixed-signal PHYs such as SerDes, USB, and DDR.
Cooperate with the analog circuit design team to ensure high efficiency and quality for analog layout design.

Desired Qualifications

Work experience in PERC runs is a plus.
Work experience in FinFET layout is a plus.
Work experience in ESD/Latch-up is a plus.
Work experience cooperating with a digital place-and-route team is a plus.
Teamwork and self-motivation are essential.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Custom Layout Design Engineer

Position Description:

Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
Responsible for custom layout top level hierarchy floorplan for blocks/powers
Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.

Position Requirements:

BSEE degree with 2+ years of applicable experience in analog/custom layout of advanced technology nodes
Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
Proficient with EMIR tools, like Voltus-FI
Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
Fundamental understanding of IC design technology and process/methodology
Essential that the individual demonstrates good teamwork and self-motivation
Good communication skills in English
Work experience in PERC run is a plus
Work experience in FinFET layout is a plus
Work experience in ESD/Latch-up is a plus
Work experience in cooperation with digital P&R team is a plus

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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