AI for Smarter IP Design Workflows

Cadence expands ChipStack AI Super Agent with a new agent for RTL Generation and Early PPA optimization. New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff-grade quality and performance, validated in early trials with Honda Published on 09/22/2026 at 09:02 am EDT Business Wire Cadence (Nasdaq: CDNS) today introduced a new agent for Cadence(R) ChipStack(TM) AI Super Agent that automates front-end digital design and verification - covering power, performance and area (PPA)-driven spec-to-RTL generation, RTL analysis, and refinement; all from natural language prompts. Building on the industry's first agentic workflow for front-end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high-quality RTL creation and optimization. In early evaluations, the RTL Generation Agent delivered an average of 24% area reduction and 18% power reduction versus pure foundation model code generation, while ensuring 100% functionally accurate RTL, underscoring the industry's most comprehensive agentic workflow for PPA-focused high-performance digital design and verification. Building on the industry's first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization. "These latest agentic AI advancements take us from AI-assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies," said Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. "By pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence's leadership in AI-driven, end-to-end chip design." Cadence's transformational approach to applying agentic AI to engineering design is founded on a hierarchy of solutions - super agents orchestrate task-specific agents, which in turn use trusted electronic design automation (EDA) software, optimized for agentic workflows. The new RTL Generation Agent converts high-level specification into production-ready RTL optimized for PPA. Customer Validation from Honda Early collaborations with Honda R&D demonstrate how these agentic AI capabilities translate into real-world PPA and productivity gains on next-generation SoCs. Honda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety-critical requirements and tight power and cost envelopes demand highly optimized RTL. "As a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent's RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development," said Tomoya Nishino, chief engineer and general manager, Digital Engine Development Division, SDV R&D Center, Honda R&D Co., Ltd. Smarter RTL Updates and Early PPA Insight In addition to new RTL creation within the RTL Generation Agent, Cadence is introducing technology for design updates to existing RTL based on new requirements. This RTL upgrade flow brings AI automation to accelerate RTL revision, enabling customers to rapidly adapt legacy RTL to new architecture requirements, new PPA targets and new functional requirements. Engineers describe changes at a high level, and the agents carry out the updates while analyzing and verifying PPA and functionality. Advancing Cadence's Agentic AI Vision These enhancements build on Cadence's "Design for AI and AI for Design" strategy highlighted at CadenceLIVE and Computex, further extending the company's leadership in AI-driven chip design. From the initial ChipStack AI Super Agent launch through June's announcement of the industry's first fully autonomous virtual engineer for chip design, and now today's RTL Generation Agent, Cadence continues to expand the scope of agentic workflows across the design stack. Together with the broader ChipStack, InnoStack and ViraStack AI Super Agent portfolio, they advance a scalable platform that applies AI across digital, analog and verification domains. Availability The expanded ChipStack and InnoStack AI Super Agent capabilities are expected to be available to select early-access customers in the fourth quarter of 2026. About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design(TM) strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2025, Cadence was recognized by Fortune as one of the world's top 100 best companies to work for. Cadence solutions offer limitless opportunities. (C) 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. View source version on businesswire.com: https://www.businesswire.com/news/home/20260922021231/en/ (C) Business Wire - 2026

Cadence subsystem for PCIe 6.0 architecture achieves first-pass PCI Express specification compliance. Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI/HPC customers. Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express(R)(PCIe(R) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG(R) compliance workshop held in late July. The workshop marked the industry's first official event for PCIe 6.0 specification compliance testing, with Cadence's x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT/s. The complete Cadence subsystem solution, comprising both PHY and controller, successfully passed all official PCIe 6.0 compliance specification tests and is on PCI-SIG's Integrators List. "PCI Express is a crucial scale-up interconnect for AI/HPC data centers and AI factories, and Cadence's subsystem for the PCIe 6.0 specification delivers best-in-class performance with among the lowest power in the industry," said Marc Loinaz, vice president of research and development for high-performance PHY, Silicon Solutions Group at Cadence. "This first-pass compliance success validates our complete PHY and controller solution and gives customers confidence that our technology is fully interoperable and ready for production." The milestone underscores the importance of early ecosystem collaboration in bringing new standards to market. Cadence worked closely with PCI-SIG, test equipment providers, and industry partners in the months leading up to the official compliance workshop, conducting interoperability testing to identify and resolve potential issues before the formal evaluation. "As PCIe 6.0 technology enables the next wave of AI and high-performance computing systems, rigorous compliance and interoperability testing are essential for ecosystem success," said Brig Asay, General Manager, Network Data Center, Keysight Technologies. "Cadence's first-pass compliance achievement reflects both the quality of its PCIe 6.0 subsystem implementation and the effectiveness of comprehensive validation using Keysight's test and measurement solutions. We are pleased to support industry leaders in accelerating PCIe 6.0 technology deployment with confidence." "Cadence is a long-standing PCI-SIG member helping to further PCIe technology adoption," said Al Yanes, president and chairperson of PCI-SIG. "Cadence's PCIe 6.0 compliance milestone plays a role in the continued advancement of PCIe technology architecture." PCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, where the standard is used for accelerator cards, network interfaces, and storage devices. The interface is expected to see wide adoption in data center and AI infrastructure, with broader deployment in automotive and enterprise systems following as the ecosystem matures. "Positron AI has licensed Cadence's SerDes IP for the PCIe 6.0 specification for our AI inference accelerator chip," said Thomas Sohmers, CTO at Positron AI. "Cadence's complete PCIe 6.0 subsystem built in silicon and robust interoperability testing give us confidence that our PCIe 6.0 interface will meet the high-bandwidth connectivity demands of our transformer workloads." Key features of Cadence's PCIe 6.0 technology solution include: * Complete subsystem solution with PHY and controller built in silicon * ADC and DSP-based equalization * Firmware-optimized SerDes operation * Multi-protocol flexibility and support * Optimized for low power, including support for the latest PCI-SIG engineering change notices (ECNs) * Certification for x8 configuration on TSMC N3 process PCI-SIG has continued to advance the PCIe standard to meet the needs of advanced HPC and AI workloads. Cadence offers a broad portfolio of PCIe technology solutions up to the PCIe 7.0 specification. Cadence's complete subsystem solution for PCIe 6.0 technology, including PHY and controller, is available now for SoC providers to design in. For more information on Cadence IP for PCIe 6.0 technology, visit the Cadence PCIe 6.0 and CXL PHY product page or download the Design IP brochure.

Cadence has announced a collaboration with Analog Devices to develop the latest generation of SHARC automotive audio processors. The partnership integrates Cadence's Tensilica DSP architecture into ADI's ADSP product family, enabling enhanced audio experiences and AI capabilities for automotive platforms. ADI is introducing the ADSP-SC84x/2184x platform, featuring the new SHARC-FX processor core developed jointly with Cadence. Built on 16nm process technology, the platform delivers five times higher performance compared to the previous generation. The SHARC-FX core supports AI-driven audio processing, including noise cancellation and voice assistance. The processors power various automotive applications, including advanced driver alerts, road noise cancellation, immersive 3D audio, and voice processing. The architecture enables on-chip AI workloads whilst maintaining real-time performance for safety-critical automotive systems.