Apple

Designs phones, computers and their operating systems

Mixed Signal RTL Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNo salary listedIn-person

About the Job

Requirements

A Bachelor of Science degree in Electrical Engineering is required.
At least 10 years of relevant experience is preferred.
Deep knowledge of RTL design, Verilog, and SystemVerilog is required.
Good knowledge of mixed-signal concepts and algorithm development is required.
Experience working with physical design teams is required.
Knowledge of front-end tools, including Verilog simulators, linters, and clock-domain-crossing checkers, is required.
Knowledge of synthesis, static timing, and design-for-test is desirable.
Knowledge of SystemVerilog assertions, checkers, and other design-verification techniques is desirable.
Knowledge of scripting languages is required; Perl and Python are desirable.
Good communication and presentation skills are required.

Responsibilities

Specify, design, and help verify and perform laboratory bring-up of advanced mixed-signal circuits on the digital side.
Write RTL code for blocks specified by the engineer or others for advanced mixed-signal circuits.
Write detailed design specifications.
Collaborate closely with the system architect, circuit designers, and design-verification engineers.
Use formal tools, including lint, clock-domain crossing, and reset-domain crossing tools, to ensure RTL quality.
Support design verification to ensure bug-free silicon.
Work with the physical-design team on timing closure for the designs.
Support silicon bring-up.

Summary

Specify, design and help in the verification and lab bring up of advanced mixed-signal circuits (digital side).

Minimum Qualifications

Bachelor's of Science in Electric Engineering with 10+ years of relevant experience preferred

Preferred Qualifications

Deep knowledge of RTL design Deep knowledge of Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm development Working experience with physical design teams Good Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers) Good knowledge of synthesis, static timing , DFT is a plus Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus Good knowledge of scripting languages. Perl and Python are plusses. Good communication and presentation skills

Description

In this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed signal circuits. You will be writing detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.Formal tools like LINT, CDC,RDC will be used to guarantee RTL quality. Supporting design verification to ensure bug free silicon. Working with the PD team for timing closure for your designs and finally supporting silicon bring up

About the Company

Apple

Designs phones, computers and their operating systems

Apple designs and sells consumer electronics, from iPhone smartphones and Mac computers to tablets and wearable devices. Its operating systems manage apps and built-in functions for communication and work, while iCloud stores files and synchronizes data across devices. Customers buy additional digital services through subscriptions such as Apple Music and Apple TV, and developers distribute software through the App Store. Apple earns money from hardware sales, subscriptions and digital transactions, selling directly to customers and through retailers and mobile carriers around the world. It was founded in 1976 and has its headquarters in Cupertino, California.

Company size: 10,001+
Company stage: IPO
Headquarters: Cupertino, CA
Founded: 1976

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