Front End RTL Designer / SoC Integration
Vertical Compute
Front End RTL Designer / SoC Integration
Vertical Compute
Chiplet-based memory-compute integration for edge AI
About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a Front-End RTL Designer to contribute to building our Vertical Compute's 3D-integrated chiplets. In this role, you will focus on top-level integration and integrating all IPs to build the AI accelerator that will demonstrate the full potential of our Vertical Integrated Memory (VIM™) technology. You will handle full SoC integration, working in close collaboration with verification and physical design teams to ensure the targeted Power, Performance, and Area (PPA) of the product.
Key Responsibilities:
Lead top-level SoC and chiplet integration, incorporating all internal and third-party IPs to build high-performance AI accelerators.
Integrate proprietary Vertical Integrated Memory (VIM™) technology with compute engines to maximize throughput and bandwidth efficiency.
Partner closely with functional verification teams to build verification environments, debug RTL issues, and ensure robust design coverage.
Collaborate with physical design teams to optimize Power, Performance, and Area (PPA), supporting synthesis, timing closure, and floorplanning.
About the team:
This role is part of the Hardware (HW) team, reporting directly to the HW Manager. You will join a collaborative and innovative team dedicated to delivering cutting-edge AI accelerator solutions and pushing the boundaries of memory and compute integration.
Chiplet-based memory-compute integration for edge AI
Vertical Compute develops chiplet-based technology that vertically integrates memory and compute to address the AI memory wall. It stacks high-aspect-ratio vertical data lanes above compute units, so data moves over nanometres instead of across long traces, improving energy use, density, and performance for AI at the edge. The company differentiates itself by co-designing memory and compute in a vertical chiplet stack to achieve higher density and lower data-transfer energy than traditional DRAM approaches, with a focus on privacy-preserving edge AI. Its goal is to move from seed funding to commercialization by building its engineering team and bringing its vertical memory-compute technology to market.
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