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Cadence Design Systems

Develops EDA software, IP, verification tools

Senior Principal Design Engineer

Hardware Validation & Testing +1Confirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

  • 12–14 years of work experience in the very-large-scale integration domain.
  • A Master's or Bachelor's degree in engineering.
  • Strong expertise in Verilog and hardware verification languages, including SystemVerilog and Specman e, with Universal Verification Methodology, Open Verification Methodology, or eRM methodologies.
  • Expertise in assertion development and closure, constraint randomization, functional coverage, code coverage, and formal verification.
  • Expertise in testbench development.
  • Strong register-transfer-level and gate-level simulation, with or without standard delay format, simulation debug skills.
  • Ability to use Perl and Tcl scripting for automation.

Responsibilities

  • Manage project schedules and delivery independently.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size
10,001+
Company stage
IPO
Headquarters
San Jose, CA
Founded
1988

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