Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Product Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

A BS or equivalent experience with at least 6 years of direct experience in DFT in EDA, CAD, or design implementation, or an MS with at least 4 years of such experience.
A solid understanding of ATPG, Scan, JTAG, IEEE 1687 (iJTAG), MBIST, and LBIST.
Awareness of the latest technologies and innovations in DFT, both in EDA and implementation.
Flexibility and adaptability to work in a highly dynamic environment and engage with key stakeholders across teams inside and outside Cadence.
Excellent communication, interpersonal, and customer collaboration skills.

Responsibilities

Help drive new product features in DFT and ATPG as part of the Modus Test Product Engineering team.
Develop product specifications and prototypes, and work closely with R&D and Product Validation teams to implement and validate features.
Work with field teams and customers to help deploy Modus by developing flows and presentations and providing hands-on debugging.

Desired Qualifications

Experience in STA, Physical Design, or silicon bring-up related to DFT is a plus.
Broad knowledge of the DFT domain and how DFT interacts with various other VLSI domains.
Hands-on experience with industry DFT EDA tools.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a highly motivated engineer to work with the Modus Test Product Engineering team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG).

What You'll Be Doing

Be part of a team that is going to help drive new product features in DFT & ATPG
Develop product spec, prototype and work closely with R&D & Product Validation teams in implementation & validation of such features
Work with field team and customers in helping deploy Modus by developing flows, presentations & hands-on debug

What We Need To See

BS (or equivalent experience) with 6+ years or MS with 4+ years of direct experience in DFT either in EDA, CAD or design implementation
Solid understanding of ATPG, Scan, JTAG, IEEE 1687 (iJTAG), MBIST & LBIST
Need to be aware of latest technologies & innovations in DFT both in EDA and implementation
Experience in STA, Physical Design, Silicon bringup related to DFT is a plus
Flexibility/adaptability for working in a highly dynamic environment and engaging with key stakeholders across various teams within and outside of Cadence
Excellent communication, interpersonal and customer collaboration skills

Ways To Stand Out From The Crowd

Broad knowledge of DFT domain & how DFT interacts with various other VLSI domains
Hands-on experience with DFT EDA tools in the industry

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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