Senior SoC Physical Design Engineer - AI/ML, ASICS Engineering

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

General Summary:

Experience: 4–5 years

Job Overview:

We are looking for a Physical Design Engineer with strong SoC/ASIC implementation experience and exposure to AI/ML-based methodologies for Physical Design optimization and automation. The engineer will work on complex SoC designs, driving implementation and improving Power, Performance and Area (PPA) using advanced automation and data-driven techniques.

Key Responsibilities:

• Own Physical Design implementation from floorplanning through PnR, CTS, routing and timing closure.
• Work on complex SoC/IP blocks targeting aggressive PPA goals.
• Debug timing, congestion, power and physical design issues and drive design convergence.
• Develop Python/TCL-based automation for Physical Design flows and productivity improvements.
• Apply AI/ML techniques to Physical Design problems such as floorplanning, placement, optimization, PPA prediction or design-flow automation.
• Collaborate with RTL, STA, DFT, CAD and other SoC teams through tapeout.

Required Skills:

• 4–5 years of hands-on ASIC/SoC Physical Design experience.
• Strong knowledge of Floorplanning, Placement, CTS, Routing, STA and Timing Closure.
• Good understanding of PPA optimization, low-power design and physical/signoff verification.
• Hands-on experience with tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk or Voltus. Current Qualcomm Physical Design openings similarly emphasize these toolsets and end-to-end PD/signoff expertise.
• Strong scripting/programming skills in Python and TCL.
• Practical exposure to AI/ML, Machine Learning algorithms, GenAI or data-driven optimization applied to VLSI/EDA/Physical Design.
• Knowledge of optimization, graph algorithms or computational geometry is an advantage. An internal Global SoC Central Physical Design requirement specifically identifies Python, geometry packages, optimization algorithms, SoC knowledge and AI/ML background as relevant skills.
• Experience with advanced technology nodes is preferred.

Preferred Profile:

Candidates combining strong core Physical Design fundamentals + Python automation + hands-on AI/ML exposure will be highly preferred. Experience developing AI/ML-assisted EDA flows, PPA optimization techniques, synthetic-data generation, or GenAI applications for chip design would be particularly relevant.

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