Packaging Technology Integration – Senior Staff Engineer - Hardware Engineering

Join this team focused on RF Front End Modules for the Cellular and Wireless Data markets. You will be part of the Business Unit Engineering organization, working closely with Design, Test, NPI Planning, Program Management, Product Marketing, Quality, Reliability, Operations, Customer Engineering, Supplier Quality, and internal and external manufacturing partners.

This position requires a senior technical specialist who owns end‑to‑end packaging technology and product integration, including wafer pre‑assembly (wafer BE), spanning technology development, chip‑to‑package co‑design, NPI, high volume manufacturing (HVM) interaction, and customer lifecycle support, to deliver robust and scalable solutions.

Responsibilities:

• Operate as a senior technical lead in a global, cross‑functional matrix, driving technology readiness, execution, and product timelines.
• Drive development and integration of Si and GaAs packaging processes from wafer‑level interconnect and RDL through Cu pillar bumping, singulation, and flip‑chip assembly.
• Lead and qualify wafer singulation technologies, including stealth dicing and plasma dicing, with ownership of die strength, edge quality, yield, and reliability tradeoffs.
• Drive substrate and assembly solutions for RF SiP applications.
• Own end‑to‑end technology integration into products, including wafer‑level and package‑level risk assessment, mitigation, and release readiness.
• Develop and maintain packaging design rules aligned with manufacturing and reliability constraints.
• Leverage FAB BEOL process knowledge to manage upstream impacts on bumping, singulation, and pre‑assembly.
• Serve as the technical interface to OSATs, leading technology transfer, qualification, and new OSAT bring‑up from development through production.
• Drive SPC, FMEA, PCN, change control, audits, and benchmarking to ensure smooth ramp and HVM stability.
• Own yield, quality, throughput, and reliability improvements to ensure successful ramp and sustained HVM product integrity.
• Plan and execute DOE to optimize bump, die sort, yield, and CPI performance.
• Lead failure analysis, root cause resolution, and reliability learning during NPI and HVM.
• Support customer NPQ, RMA analysis, and direct customer technical communication.
• Contribute to value engineering and cost reduction initiatives.
• Explore and evaluate future 2.5D packaging technologies, assessing feasibility, integration risks, and manufacturing readiness.

Qualifications:   

• Master’s degree in mechanical, Materials, Chemical, or Electrical Engineering; PhD preferred.
• 10+ years’ experience in semiconductor packaging, preferably RF modules / SiP.
• Demonstrated ownership across technology development, NPI, HVM, and customer support.
• Hands‑on experience in wafer pre‑assembly / wafer BE, including Cu pillar or micro‑bump bumping, wafer singulation (stealth dicing, plasma dicing), and die sort.
• Demonstrated ability to debug and resolve wafer‑level yield, die integrity, and reliability issues impacting downstream assembly and HVM.
• Strong understanding of packaging materials, process interactions, failure mechanisms, and reliability.
• Hands‑on experience with tier‑1 foundries and OSATs.
• Working knowledge of industry standards (IPC, JEDEC, IEEE, ISO, ANSI).
• Experience in qualification, reliability testing, and failure analysis.
• Solid foundation in statistics, SPC, and FMEA.
• Strong cross‑functional communication and leadership skills.
• Willingness to travel internationally (~once per quarter).

Minimum Qualifications:

• Bachelor’s degree in engineering or related field and 6+ years of relevant experience; or
• Master’s degree in engineering or related field and 5+ years of relevant experience; or
• PhD in Engineering or related field and 4+ years of relevant experience.