C

Cadence Design Systems

Develops EDA software, IP, verification tools

Lead Verification Engineer

Full-Time
No salary listed
Mid
Bachelor's, Master's
Noida, Uttar Pradesh, India+1 moreMore locations: Bengaluru, Karnataka, India
In Person

About the job

Requirements
  • A degree in Electrical Engineering, Electronics, or Computer Science, specifically B.Tech, Bachelor of Engineering, M.Tech, or Master of Engineering.
  • At least 3 years of relevant experience.
  • A strong understanding of hardware description languages, including Verilog and/or VHDL.
  • Prior experience in emulation or Unified Power Format is preferred.
  • Working knowledge of electronic design automation tools, especially Palladium, with a focus on debugging design and verification problems.
  • Experience with process automation using scripting.
  • Experience with SystemVerilog, C++, and Universal Verification Methodology.
  • Experience with functional verification of complex digital systems, such as system-on-chip verification, using a hardware verification language such as SystemVerilog.
  • Strong written, verbal, and presentation skills.
  • Good communication and interpersonal skills, with the ability to work collaboratively.
  • Ability to establish close working relationships with customer peers and management.
  • Ability to work effectively across functions and geographies and operate with integrity.
Responsibilities
  • Validate products and key Palladium technologies, including Unified Power Format.
  • Verify various upcoming features in Palladium.
  • Manage the current set of regressions.
  • Participate in technical discussions, including functional specification and test plan reviews.
  • Review and guide team members on technical deliverables.
  • Take responsibility and accountability for the quality of releases and features for Palladium emulation technology.
  • Mentor junior team members.
  • Contribute to improving existing emulation validation and verification flows.
Desired Qualifications
  • Prior experience in emulation or Unified Power Format.

About the company

Cadence Design Systems provides software, hardware, and IP for electronic design automation (EDA) to help customers design advanced semiconductor chips and electronic systems. Its tools cover system-level design and verification, digital and analog IC design, and custom design flows, with IP offerings like Tensilica processors and DSP cores available for licensing. It differentiates itself by offering an end-to-end EDA portfolio and deep collaboration with industry leaders across implementation, verification, and IP. The goal is to help customers bring sophisticated silicon and electronics to market faster while reducing risk and improving productivity across AI, audio, video, and automotive applications.

Company Size

10,001+

Company Stage

IPO

Headquarters

San Jose, California

Founded

1988

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Simplify's Take

What believers are saying

  • Honda R&D is evaluating Cadence's RTL Generation Agent for automotive SoCs.
  • Cadence's Q2 2026 revenue rose 24.2%, and backlog hit $8.1 billion.
  • Positron AI licensed Cadence PCIe 6.0 SerDes IP for an inference accelerator.

What critics are saying

  • Cadence sued Suzhou Tianshun in August 2026 over alleged cracked software use.
  • Cadence still fights Yunjing Intelligent Innovation's copyright case filed in 2025.
  • OpenAI and Anthropic commoditize Cadence's RTL creation, crushing pricing power by 2027.

What makes Cadence Design Systems unique

  • Cadence's September 22, 2026 ChipStack AI agent turns specs into production-ready RTL.
  • Cadence's September 2026 PCIe 6.0 subsystem passed first-pass compliance on TSMC N3.
  • Cadence and TSMC expanded September 23, 2026 collaboration across N3, N2, A16, and A14.

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Benefits

Health Insurance

Dental Insurance

Life Insurance

Flexible Work Hours

Paid Vacation

Paid Sick Leave

Growth & Insights and Company News

Headcount

6 month growth

↑ 0%

1 year growth

↓ -1%

2 year growth

↓ -1%
Yahoo Finance
Oct 1st, 2026
Synopsys vs Cadence: Which chip design software giant offers better value after Ansys acquisition?

Synopsys and Cadence Design Systems dominate the chip design software market, yet both stocks have fallen over the past year despite strong semiconductor sector performance. Synopsys generated $9.42 billion in revenue, growing 42.4% last quarter largely through its Ansys acquisition. However, the deal brought significant costs: operating margin sits at 14.52%, total debt reached $10.84 billion, and return on equity fell to 3.66%. Cadence achieved 24.2% organic revenue growth to $5.84 billion without major acquisitions. It maintains a 28.58% operating margin and carries just $2.65 billion in debt. The valuation gap reflects these differences. Cadence trades at over 15 times revenue versus Synopsys's 8.5 times. On trailing earnings, Synopsys appears more expensive at 73 times versus 65 times for Cadence. Both companies benefit from customer lock-in, as switching design tools requires costly revalidation and retraining. AI chip designers have strengthened demand for both vendors. At Q2 2026, 85 hedge funds held Synopsys shares worth $4.1 billion, whilst 69 held Cadence positions valued at $3.2 billion.

Cadence
Sep 29th, 2026
Cadence BETA CAE announces the release of 2025.2.3 version of its software suite.

Cadence BETA CAE announces the release of 2025.2.3 version of its software suite. About this release. Cadence Design Systems, Inc. officially announce the third hot fix release of 2025.2 for the Cadence BETA CAE ANSA Pre-Processor, EPILYSIS FEA Solver, META Post-Processor, FATIQ Platform, SPDRM Software and KOMVOS SDM Console with critical bug fixes. Known Issues Resolved in ANSA Pre-Processor. Focusing on "Isolate flanges proximity" functionality, unmeshed faces thickness would wrongly be disregarded, and solid thickness value would be used instead. Batch Meshing Certain CFD anisotropic mesh cases could occasionally lead to an unexpected termination when setup was taking place via ANSA Parameters. Volume Meshing Abrupt changes in layer heights could occur in corners where layers would connect to inclined sides. Connections and Assembly Realizing a Y-JOINT-SHELL with 'Preserve mesh' options could produce wrong results. In addition, after executing 'Erase FE' of a SPIDER2 connection realized on the 'Top Area' of a stamp feature, the elements filling the hole would be added to the 'Rest Area' of the stamp feature, causing a subsequent realize action to fail. Compare Tool Opening the 'Compare Tool' unexpectedly would cause tabbed 'Models List' to disappear. Decks - General Unexpected software abortion would also take place when using the '[STRIKEOUT:>' syntax to get the ID of a material used in a material reference field in a PART_COMPOSITE property list (i.e. MID1]>MID). Focusing on material DB and "Copy to List" command, the unmatched materials would wrongly get other IDs, while no overlap would exist. The calculation of the resultant force would be incorrect when the 'Resultant Force' tool was applied to DLOADs with load type Hydrostatic Pressure (HP) and the 'Magnitude > Loads' option was deactivated in the presentation parameters. The 'Compress' function would wrongly delete DEFINE_BOX entities ignoring the fact that they were used in the model. A contact entity consisting of a flex body and a rigid body having several geometries would erroneously be exported as several contact definitions with the same name and that would create a conflict in ADAMS. Focusing on flex bodies, while exporting models in ADAMS Solver Dataset (.adm) format, the .mtx data of flex bodies would not be written out on Windows O/S. Optimization In the 'Optimization' tool, the functions 'RSM Improve' and 'RSM Optimization' would occasionally not recognize the ML toolkit environment. Also, the 'Optimization' tool would falsely output integer design variable values (e.g. MID, PID) as float type, when symbolic variables option was activated. Focusing on OptiStruct, DTPG card would not be correctly output as expected. Task Manager ANSA Pre-Processor would terminate unexpectedly when long comments were added to the task manager. Known Issues Resolved in META Post-Processor Focusing on 2D plots, META Post-Processor would abort when double-clicking the X-coordinate of a curve point created by 'Bore Distortion Analysis.' In addition, unexpected termination could occur when deleting META variables. Curves from .h5 files were not read properly. Abaqus fastener coupling visibility actions were not working as expected. Results on transformed includes were not displayed correctly on the corresponding transformed geometry. Also, thickness and MID information were neither read, nor displayed properly in META Post-Processor. Math Operations on Field Data Calculations with tensor results for 'Strain Gauges' would not take large translations/rotations into account. Project Files and METADB Script function 'results.PrimaryResultsList' would not return the correct information for METADBs converted from d3plot. Images and Video Handling Scale points for 'Plot Tracked Features' could not be picked on the video and the model. Read Results When loading a curve from a column ASCII format file using the 'Bar Plot from Column' or 'Bar Plot from Row' format options, the corresponding command recorded in the session was not automatically recognized as a valid filename. META Post-Processor would freeze when selecting a results file through file path recommendations using only the keyboard. META Post-Processor was unable to recognize distinct subcases in H3D files during result selection. Managing Curve Data META Post-Processor would terminate unexpectedly in cases of binout files with rbdout section. Wrong vector fringe would be generated in Internal type boundaries of Fidelity Flow cases. Annotations Annotations on selection variables were not properly evaluated if 'Append Pointers' option was active. Also, creating annotations on picked entities from screen could possibly lead to abnormal termination. Pressing Ctrl+N following export to JT format would lead to an unexpected termination. Regarding Spreadsheet Editor, extending LOG10 function to several cells led to corruption of the function. The same corrupted behavior was noticed while loading XLSX spreadsheet with extended LOG10 formulas. In addition, when saving a property's HTML Laminate Report, the report was saved without the associated images in the output folder. Known Issues Resolved in FATIQ Platform Calculations - Deterministic Loads Multiple subcases in deterministic loads would not be handled properly. Known Issues Resolved in KOMVOS SDM Console The KOMVOS SDM Console profile name would not be updated in the main panel upon reconnecting to SPDRM Software. Data Management - Lifecycle Business Rules The evaluation of conflict resolution policy through API now operates as expected. Known Issues Resolved in SPDRM Software Performance This release introduces significant enhancements to the SPDRM Software server, boosting its ability to handle high concurrency and demanding workloads. Key improvements include: * Enhanced stability: Advanced mechanisms ensure consistent and reliable operation, even under extreme load conditions. * Greater resilience: Optimized handling of concurrent requests maintains responsiveness during peak demand. The efficiency in processing rapid concurrent uploads, queries and exports has increased by 50%. Furthermore, the new release showcases efficient resource utilization, optimized I/O handling, and robust concurrency control, which are the key factors for scaling distributed systems, specifically: * 40,000+ structured CAE objects (metadata and file) saved in 15 minutes * 350 concurrent workers executing read/write operations with consistent throughput * This stress test scenario is equivalent to and ensures that 1,000+ active users can effectively perform daily business tasks connected to SPDRM Software Where to Download From You can find this release on Cadence Downloads, dated as of September 22, 2026. Customers who are served by a local business agent should contact the local support channel for software distribution details. Visit Cadence Softwae Downloads.

Yahoo Finance
Sep 23rd, 2026
Cadence CEO sells $1.1M in shares to cover tax obligations, retains $69M stake

Cadence Design Systems CEO Anirudh Devgan sold 3,779 shares on 17 September 2026, valued at $1.1 million, according to an SEC filing. The transaction was non-discretionary, executed solely to cover tax withholding obligations from vesting equity awards. Following the sale, Devgan retains direct ownership of 247,201 shares, worth $69.40 million at the 17 September market close. The disposed shares represented approximately 2% of his holdings. Cadence, a market leader in electronic design automation software, generated $5.8 billion in trailing twelve-month revenue. The company's revenue rose 21% year-over-year in the first half of 2026, whilst net income increased 62% to $703 million during the same period.

MarketScreener
Sep 22nd, 2026
Cadence expands ChipStack AI Super Agent with a new agent for RTL Generation and Early PPA optimization.

Cadence expands ChipStack AI Super Agent with a new agent for RTL Generation and Early PPA optimization. New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff-grade quality and performance, validated in early trials with Honda Published on 09/22/2026 at 09:02 am EDT Business Wire Cadence (Nasdaq: CDNS) today introduced a new agent for Cadence(R) ChipStack(TM) AI Super Agent that automates front-end digital design and verification - covering power, performance and area (PPA)-driven spec-to-RTL generation, RTL analysis, and refinement; all from natural language prompts. Building on the industry's first agentic workflow for front-end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high-quality RTL creation and optimization. In early evaluations, the RTL Generation Agent delivered an average of 24% area reduction and 18% power reduction versus pure foundation model code generation, while ensuring 100% functionally accurate RTL, underscoring the industry's most comprehensive agentic workflow for PPA-focused high-performance digital design and verification. Building on the industry's first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization. "These latest agentic AI advancements take us from AI-assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies," said Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. "By pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence's leadership in AI-driven, end-to-end chip design." Cadence's transformational approach to applying agentic AI to engineering design is founded on a hierarchy of solutions - super agents orchestrate task-specific agents, which in turn use trusted electronic design automation (EDA) software, optimized for agentic workflows. The new RTL Generation Agent converts high-level specification into production-ready RTL optimized for PPA. Customer Validation from Honda Early collaborations with Honda R&D demonstrate how these agentic AI capabilities translate into real-world PPA and productivity gains on next-generation SoCs. Honda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety-critical requirements and tight power and cost envelopes demand highly optimized RTL. "As a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent's RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development," said Tomoya Nishino, chief engineer and general manager, Digital Engine Development Division, SDV R&D Center, Honda R&D Co., Ltd. Smarter RTL Updates and Early PPA Insight In addition to new RTL creation within the RTL Generation Agent, Cadence is introducing technology for design updates to existing RTL based on new requirements. This RTL upgrade flow brings AI automation to accelerate RTL revision, enabling customers to rapidly adapt legacy RTL to new architecture requirements, new PPA targets and new functional requirements. Engineers describe changes at a high level, and the agents carry out the updates while analyzing and verifying PPA and functionality. Advancing Cadence's Agentic AI Vision These enhancements build on Cadence's "Design for AI and AI for Design" strategy highlighted at CadenceLIVE and Computex, further extending the company's leadership in AI-driven chip design. From the initial ChipStack AI Super Agent launch through June's announcement of the industry's first fully autonomous virtual engineer for chip design, and now today's RTL Generation Agent, Cadence continues to expand the scope of agentic workflows across the design stack. Together with the broader ChipStack, InnoStack and ViraStack AI Super Agent portfolio, they advance a scalable platform that applies AI across digital, analog and verification domains. Availability The expanded ChipStack and InnoStack AI Super Agent capabilities are expected to be available to select early-access customers in the fourth quarter of 2026. About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design(TM) strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2025, Cadence was recognized by Fortune as one of the world's top 100 best companies to work for. Cadence solutions offer limitless opportunities. (C) 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. View source version on businesswire.com: https://www.businesswire.com/news/home/20260922021231/en/ (C) Business Wire - 2026

Trener
Sep 22nd, 2026
Trener Robotics raises $32M Series A to bring Physical AI and software-defined control to industrial automation – Trener Robotics

The fresh capital will scale deployment of Acteris, an agentic AI platform that transforms industrial robots into intelligent, self-learning teammates