ASIC Design and Integration Engineer - Silicon Security

Summary

Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art hardware defenses that prevent complex side channel attacks and ensure the integrity of our customers' most sensitive data across Apple's product line. Our work spans cryptographic engines, side channel attack monitors, data protection logics etc that make Apple devices the most secure consumer electronics in the world.

Minimum Qualifications

BS in Electrical Engineering, Computer Engineering or a relevant field and 3 years of industry experience 3 years of RTL design experience using Verilog or SystemVerilog.

Preferred Qualifications

Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and verification. Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability. Background in cryptography and cryptographic algorithm implementation. Experience with hardware security concepts including key management, physical attack and countermeasures. Experience with clock and reset architecture at the subsystem level Strong knowledge of AMBA bus protocols (AXI, AHB, APB). Experience with hardware security concepts including key management, physical attack and countermeasures

Description

As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will include: • Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time • Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met. • Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns • Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis. • Leveraging AI-assisted tools to enhance design quality and productivity.