Senior Staff Physical Design Engineer

Responsibilities

We are seeking an experienced Sr. Staff Physical Design Engineer to lead end‑to‑end physical design for complex SoCs and large digital blocks. The role involves ownership of floorplanning, placement, CTS, routing, timing closure, and physical sign‑off across MMMC scenarios.

You will drive STA, IR/EM, power integrity, and DRC/LVS sign‑off, support ECOs, and enhance P&R methodologies through automation. Close collaboration with RTL, STA, DFT, and verification teams is key, along with mentoring junior engineers. You will focus on:

Physical Design & Implementation

• Own end‑to‑end place‑and‑route execution for complex SoCs and large digital blocks
• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
• Drive timing closure across multi‑mode, multi‑corner (MMMC) scenarios
• Solve challenging setup/hold, clocking, and CDC‑related timing issues

Sign‑off & Quality Closure

• Perform static timing analysis (STA) and constraint debugging at block and full‑chip level
• Lead IR drop, EM, and power integrity analysis, and implement corrective actions
• Execute and debug physical verification (DRC/LVS) to achieve clean sign‑off
• Support ECO flows, late‑stage fixes, and post‑layout optimization

Methodology & Automation

• Develop, enhance, and maintain P&R flow automation using Tcl, Python, Perl, and shell scripting
• Improve turnaround time, QoR, and repeatability through methodology enhancements
• Review and contribute to physical design guidelines and best practices

Cross‑Functional Collaboration

• Work closely with RTL design, STA, verification, DFT, and architecture teams
• Provide early physical feasibility feedback on clocking, floorplan, and RTL structures
• Mentor junior engineers and act as a technical point of reference within the PD team

Qualifications

• Bachelor’s degree or Master’s in Electrical / Electronics Engineering or related field
• 7+ years of experience in ASIC physical design
• Proven track record of successful ASIC tape‑outs at block or full‑chip level
• Strong hands‑on experience with:
• • Place & Route: Cadence Innovus
  • STA: Cadence Tempus
  • IR/EM: Cadence Voltus, RedHawk
  • Physical Verification: Calibre DRC/LVS
• Solid understanding of:
  • Clock tree architectures and skew management
  • Timing constraints (false paths, multicycle paths, generated clocks)
  • Power‑aware design techniques and low‑power sign‑off
• Proficiency in Linux/Unix environments and scripting for flow automation

Soft Skills & Attributes

• Strong analytical and debugging skills
• Ability to work independently with minimal supervision
• Clear communication skills for cross‑site and cross‑functional collaboration
• Quality‑driven mindset with strong ownership and accountability

Nice to Have

• Experience with mixed‑signal SoCs or power‑management related designs
• Familiarity with advanced clocking schemes and low‑frequency / high‑variation clocks
• Experience supporting post‑silicon debug or gate‑level simulation (GLS)

Company Overview

MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.

We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.

MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.

Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.

We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.