Tesla

Makes electric cars, robotaxis and grid batteries

ASIC RTL Design Engineer - Ethernet IP & SoC Integration, SI Hardware

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNo salary listed

About the Job

Requirements

A degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience is required.
At least 3 years of experience in ASIC RTL design using Verilog or SystemVerilog is required.
Strong knowledge of Ethernet protocols, including 10G, 25G, and 100G Ethernet, MAC/PHY layers, and IEEE standards is required.
Expertise in high-speed protocols, including PCIe, SerDes, or similar interfaces for data-intensive applications is required.
A solid understanding of networking concepts, including switching, routing, quality of service, and packet buffering, is required.
Hands-on experience with DMA controllers and high-performance memory access in SoC environments is required.
A proven track record in designing high-performance RTL for compute-intensive or data-heavy systems, with emphasis on pipelining and parallelism, is required.
Proficiency with AXI/AMBA bus protocols for on-chip interconnects and IP integration is required.
In-depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi-clock domain handling, is required.
Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains is required.

Responsibilities

Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high-throughput data transfer in SI hardware systems.
Develop and optimize SoC clocking architectures, including multi-domain clock distribution, synchronization, and power-efficient clock-gating techniques.
Architect and implement SoC reset mechanisms, including synchronous and asynchronous resets, reset domain crossing, and fault-tolerant recovery strategies.
Optimize high-performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines.
Integrate third-party IPs, such as Ethernet controllers and high-speed SerDes, while managing interface protocols like AXI for efficient data movement.
Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking-focused subsystems.
Perform synthesis, timing analysis, and power optimization to meet performance targets in high-speed protocols.
Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations.
Document designs, specifications, and integration guidelines to support team collaboration and future iterations.
Participate in design reviews and code reviews, and contribute to overall ASIC development flows for SI hardware.
Implement and document microarchitecture specifications tailored to networking and SoC integration, define system-level functional requirements for high-speed data handling, and deliver RTL designs optimized for SI workloads.

Category	Tesla SI
Location	Palo Alto, California
Requisition ID	258189
Type	Full-time

Job Description

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in SI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. In this specialized role, you will focus on Ethernet IP integration, SoC clocking and reset architectures, and high-performance data paths within our custom ASICs. This role is located in Palo Alto, CA or Austin, TX. You will work closely with cross-functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in SI applications. Candidates are expected to implement and document microarchitecture specifications tailored to networking and SoC integration, define system-level functional requirements for high-speed data handling, and deliver high-quality RTL designs optimized for SI workloads.

Job Responsibilities

Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high-throughput data transfer in SI hardware systems
Develop and optimize SoC clocking architectures, including multi-domain clock distribution, synchronization, and power-efficient clock gating techniques
Architect and implement SoC reset mechanisms, including synchronous/asynchronous resets, reset domain crossing, and fault-tolerant recovery strategies
Optimize high-performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines
Integrate third-party IPs, such as Ethernet controllers and high-speed serdes, while managing interface protocols like AXI for efficient data movement
Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking-focused subsystems
Perform synthesis, timing analysis, and power optimization to meet aggressive performance targets in high-speed protocols
Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations
Document designs, specifications, and integration guidelines to support team collaboration and future iterations
Participate in design reviews, code reviews, and contribute to overall ASIC development flows for SI hardware

Job Requirements

Degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience
3+ years of experience in ASIC RTL design using Verilog or SystemVerilog
Strong knowledge of Ethernet protocols (e.g., 10G/25G/100G Ethernet, MAC/PHY layers, and IEEE standards)
Expertise in high-speed protocols, including PCIe, SerDes, or similar interfaces for data-intensive applications
Solid understanding of networking concepts, such as switching, routing, QoS, and packet buffering
Hands-on experience with DMA controllers and high-performance memory access in SoC environments
Proven track record in designing high-performance RTL for compute-intensive or data-heavy systems, with emphasis on pipelining and parallelism
Proficiency with AXI/AMBA bus protocols for on-chip interconnects and IP integration
In-depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi-clock domain handling
Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains

About the Company

Tesla

Makes electric cars, robotaxis and grid batteries

Tesla makes electric cars and batteries that store power for homes and utilities, and it develops self-driving software and humanoid robots. In 2023, its Model Y became the first electric vehicle to rank as the world's best-selling car. Buyers order the Model 3 sedan, Model Y SUV, or Cybertruck pickup directly from Tesla instead of through dealers, and they charge on its Supercharger fast-charging network. It also sells Megapack and Powerwall batteries, runs a robotaxi service, and charges drivers a monthly fee for self-driving software that still needs their supervision. Tesla was founded in 2003, with Elon Musk as its lead early investor and a recognized co-founder, and it is based in Austin, Texas.

Company size: 10,001+
Company stage: IPO
Headquarters: Austin, TX
Founded: 2003

Recently Posted Jobs

Explore more opportunities at Tesla

See more jobs