Principal Advanced Node Technology Yield & Diagnostics Engineer - Advanced Semiconductor Integrated Circuit Systems Engineering

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are seeking a Principal or Sr. Staff Advanced Node Process and Yield & Diagnostics Engineer to drive yield learning, technology readiness, and manufacturing success for next-generation AI platforms built on advanced-node logic, HBM, chiplet, and 3DIC technologies. The successful candidate will lead silicon characterization, yield diagnostics, failure analysis, yield forecasting, and systematic debug while translating complex process, design, package, test, and manufacturing data into actionable business and technology decisions. This role is expected to influence architecture before silicon exists by driving pre-silicon Design-for-Yield (DFY), leveraging yield modeling, defect mechanisms, redundancy and repair strategies, HBM and chiplet partitioning tradeoffs, and manufacturability analysis to optimize yield, scalability, robustness, performance, and cost across the entire AI system stack from die to package.

Key Responsibilities:

• Perform process and yield diagnostics for advanced-node digital products across wafer fabrication, wafer sort, final test, and system-level validation.
• Lead test-chip characterization and yield learning activities by partnering with IP, Design, Process Integration, Foundry, and Product/Test Engineering (PTE) teams to accelerate technology readiness and product bring-up.
• Drive systematic failure debug and root-cause investigations using electrical test data, scan diagnosis, defect inspection data, PCM measurements, inline metrology, and failure analysis results.
• Correlate process, product, design, and test data to identify yield loss mechanisms, systematic defects, and yield excursions.
• Partner with Foundry and Process Integration teams to drive technology learning, process optimization, and yield improvement.
• Support New Product Introduction (NPI) through yield risk assessments, characterization, silicon learning, and manufacturing readiness evaluations.
• Utilize statistical analysis and data mining techniques to identify process-related yield limiters and drive corrective actions.
• Develop and maintain yield models to quantify defect-density impact, process variation sensitivity, redundancy effectiveness, and yield improvement opportunities.
• Generate and communicate yield forecasts to support technology readiness assessments, manufacturing ramp planning, supply planning, and business commitments.
• Monitor yield performance and develop dashboards, KPIs, and automated reporting solutions for manufacturing health assessment.
• Work cross-functionally with Design, DFT, IP, Product Engineering, Test Engineering, Quality, and Foundry teams to improve product robustness and manufacturability.
• Drive continuous improvement through advanced analytics, automation, and AI/ML-based yield solutions.
• Partner with Architecture, Design, and IP teams to provide early yield, manufacturability, and repairability insights during product definition and RTL planning, helping identify and mitigate yield risks before tapeout and validating yield assumptions through silicon bring-up and ramp.

Minimum Qualifications:

• M.S. or Ph.D. in Electrical Engineering, Semiconductor Physics, Materials Science, or a related field.
• 10+ years (or equivalent experience) in advanced-node semiconductor yield engineering, product engineering, process integration, technology development, or yield diagnostics, with demonstrated ownership of silicon bring-up, yield learning, and yield improvement initiatives.
• Hands-on experience with advanced semiconductor technology nodes (2nm, A14, or equivalent) and yield ramp activities.
• Strong understanding of semiconductor manufacturing processes, including lithography, etch, deposition, CMP, device integration, and interconnect technologies.
• Proven experience in yield diagnostics, process-yield correlation, systematic failure debugging, failure analysis, and manufacturing data analytics.
• Hands-on experience with test-chip characterization, silicon bring-up, and cross-functional yield investigations involving Design, IP, Process Integration, Product/Test Engineering (PTE), and Foundry teams.
• Demonstrated experience developing and applying yield models and forecasts to guide technology development, yield ramp decisions, manufacturing planning, and business commitments.
• Demonstrated ability to develop yield forecasts and scenario-based models to support technology readiness assessments, manufacturing ramp planning, and business commitments.
• Familiarity with digital product architecture, DFT methodologies, scan diagnosis, and semiconductor test flows.
• Proficiency in data analysis and visualization tools such as JMP, Yield Explorer, Python, SQL, Excel, Power BI, or equivalent.
• Strong analytical and problem-solving skills with the ability to lead complex root-cause investigations across design, process, test, and manufacturing domains.
• Excellent communication and collaboration skills with the ability to influence technical decisions across global and cross-functional teams.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

• Experience leading test-chip characterization, silicon bring-up, yield learning, and advanced-node yield ramp, including collaboration with foundry partners to drive technology learning and yield improvement.
• Experience with Design-for-Yield (DFY) methodologies, including defect-aware design, process variation analysis, redundancy, repair strategies, and manufacturability optimization.
• Ability to bridge architecture, design, and yield disciplines by translating yield learning and manufacturing constraints into actionable design recommendations and validating expected yield outcomes in silicon.
• Strong knowledge of yield diagnostics, including PCM, inline defect inspection, process control, metrology, scan diagnosis, digital failure analysis, and silicon debug techniques.
• Experience applying advanced analytics, machine learning, AI, and automation to yield analysis, root-cause investigation, and manufacturing optimization.
• Knowledge of advanced packaging, 3DIC, chiplet architectures, and DRAM/memory technologies, including yield, reliability, repair/redundancy methodologies, and high-volume manufacturing optimization.

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Pay range and Other Compensation & Benefits:

$200,000.00 - $300,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.