CPU Logic Equivalence Check Engineer - Silicon Engineering Group

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is looking for a hardworking engineer for CPU gate level verification team. In this role, the candidate would be part of Apple’s industry-leading CPU design team, working in a multi-functional role to design verification flows and ensure that our CPUs meet the highest standards for functional verification.

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience Experience with at least one of the following RTL-to-gate formal verification tools (LEC): Conformal or Formality Experience in digital logic design Experience with at least one of the following programming languages, TCL, Python, or Perl

Preferred Qualifications

The ideal candidate should possess CPU implementation and verification experience Knowledge of RTL-to-gate formal verification tools (LEC) and debug techniques, Conformal ECO, and low power structural verification tools (VCLP) Working knowledge of synthesis tools and flows and Perl and TCL scripting Ability to collaborate with cross-functional RTL/PD/DFT teams to come up with custom solutions

Description

You will own the logic equivalence check and sign-off of Apple’s high-performance CPU projects. Responsibilities include but are not limited to: • Developing and improving existing flow for logical equivalent check • Running and signing off block and top level logic equivalence checks, structural gate checks, and low power checks • Supporting the design team in block level verification runs and debug • Working closely with design/CAD teams on the methodology for verification of new features • Creating scripts to automate verification runs and track the results of our various verification checks • Working with the CAD team to further develop and enhance our verification flows • Collaborate with tool vendors on new tool features and issues