Senior Principal Design-for-Test Engineer

Responsibilities:

• As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.

• Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.

• Create test vectors or oversee their creation.

• Collaborate with physical design team to close timing in DFT mode.

• Sign-off DFT requirements are being met.

• Work with testing team to bring-up test patterns on silicon.

Requirements:

• Minimum Qualifications

• BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.

• Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs.

• DFT lead experience for complex SOC TO and Production.

• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.

Preferred Qualifications

• Experience with synthesis, STA and back-end implementation flows.

• Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.

• Solid Lab and test floor bring-up and debug experience.

• Yield estimation and test optimization.

• DFT AI mindset.