Eliyan

D2D/C2C interconnect IP licensing

Digital ASIC Design Automation & Integration Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-time

About the Job

Requirements

A bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
At least 5 years of experience in ASIC or SoC design or design automation, including hands-on experience running and analyzing lint, clock-domain crossing, or synthesis tools.
Familiarity with lint, clock-domain crossing, and reset-domain crossing tools such as VC SpyGlass or QuestaLint/CDC.
Familiarity with synthesis tools such as Genus or Fusion Compiler.
Working knowledge of SystemVerilog and the RTL front-end flow, including the ability to read violations, assess severity, and disposition findings.
Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles.
Experience building and maintaining CI/CD pipelines using Jenkins, GitLab CI, or GitHub Actions.
Authorization to work in the United States or Canada.
Ability to work on-site Monday through Friday at the Bay Area, Vancouver, or Toronto office.

Responsibilities

Define and maintain lint, CDC, and synthesis elaboration signoff criteria across all active design programs.
Build and own the waiver management system, including owner attribution, justification, expiration, and audit trail.
Analyze synthesis results for area, timing, and power regressions, and trace quality-of-results anomalies to specific RTL changes.
Collaborate with project design leads to develop and maintain project-specific rule decks, synthesis constraints, and signoff checklists.
Own RTL integration of digital IP into PHY and chip-level hierarchies, including instantiation, parameterization, hierarchy assembly, and interface consistency across IP boundaries.
Build automated integration checks for top-level connectivity, tie-off and floating-input detection, clock and reset connectivity, and interface consistency between IP and SoC.
Automate register-map and interface collateral generation using tools such as PeakRDL or IP-XACT, and keep RTL, firmware headers, and documentation in sync.
Own IP release packaging and delivery, including versioned collateral, dependency tracking, reproducible builds from a tagged release, and handoff evidence for internal and customer deliveries.
Run lint, CDC, RDC, and elaboration at full-chip scope, and drive cross-IP and integration-level findings to closure with the owning designers.
Own the Jenkins-based CI pipeline for RTL quality, including lint, CDC, RDC, elaboration, synthesis, and static timing analysis.
Build the development-to-release promotion pipeline with automated gating, clean-run qualification, and handoff evidence generation.
Develop per-project dashboards for quality-of-results tracking, regression visibility, and release readiness.
Develop LLM-based violation-triage pipelines that classify lint and CDC output, suppress known-benign patterns, and surface real issues with context.
Build automated pull requests with violations pre-filtered, grouped, and annotated for designer review.
Implement spec-to-RTL consistency checking and CI-integrated documentation generation using LLM-driven pipelines.
Benchmark AI output quality, measure false-negative rates, and establish guardrails the design team can trust.

Desired Qualifications

Experience building waiver management systems, violation databases, or design-quality dashboards.
Experience with register-map automation and IP packaging standards such as PeakRDL, SystemRDL, or IP-XACT.
Knowledge of UPF and power intent.
Knowledge of static timing analysis.
Practical experience with LLM APIs or agent frameworks such as Anthropic Claude or OpenAI, applied in a production or team-facing context.
Hands-on experience integrating and releasing digital IP, including hierarchy assembly, connectivity closure, versioned collateral, and handoff to internal or external consumers.
Exposure to PHY, SerDes, die-to-die interconnect, or chiplet-based SoC design.
Open-source contributions to design automation, hardware verification, or developer tooling.

Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL

On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON

Full-Time - Equity Participation - Comprehensive Benefits

ABOUT THE ROLE

Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.

We are looking for an engineer who can own the intersection of design quality, automation, and design integration. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers.

Design quality and automation are the core of this role. IP and chip-level integration ownership is scope you can grow into as you ramp — we're looking for someone who wants it.

KEY RESPONSIBILITIES

Design Quality & Signoff

Define and maintain lint, CDC, and synthesis elaboration signoff criteria across all active design programs.

Build and own the waiver management system — structured flow with owner attribution, justification, expiration, and audit trail.

Analyze synthesis results for area, timing, and power regressions; trace QoR anomalies to specific RTL changes.

Collaborate with project design leads to develop and maintain project-specific rule decks, synthesis constraints, and signoff checklists.

IP & Chip Integration

Own RTL integration of digital IP into PHY and chip-level hierarchies — instantiation, parameterization, hierarchy assembly, and interface consistency across IP boundaries.

Build automated integration checks: top-level connectivity, tie-off and floating-input detection, clock and reset connectivity, and interface consistency between IP and SoC.

Automate register map and interface collateral generation (e.g. PeakRDL, IP-XACT) and keep RTL, firmware headers, and documentation in sync.

Own IP release packaging and delivery — versioned collateral, dependency tracking, and reproducible builds from a tagged release, with handoff evidence for internal and customer deliveries.

Run lint, CDC, RDC, and elaboration at full-chip scope, and drive cross-IP and integration-level findings to closure with the owning designers.

Flow Automation and CIC

Own the Jenkins-based CI pipeline for RTL quality: lint, CDC, RDC, elaboration, synthesis, and STA.

Build the dev-to-release promotion pipeline with automated gating, clean-run qualification, and handoff evidence generation.

Develop per-project dashboards for QoR tracking, regression visibility, and release readiness.

AI-Augmented Tooling

Develop LLM-based violation triage pipelines that classify lint and CDC output, suppress known-benign patterns, and surface real issues with context.
Build automated pull requests with violations pre-filtered, grouped, and annotated for designer review.
Implement spec-to-RTL consistency checking and CI-integrated documentation generation using LLM-driven pipelines.
Benchmark AI output quality, measure false-negative rates, and establish guardrails the design team can trust.

MINIMUM REQUIREMENTS

Bachelors, Masters or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

5+ years in ASIC or SoC design or design automation, with hands-on experience running and analyzing lint, CDC, or synthesis tools.

Familiarity with Lint/CDC/RDC tools like VC SpyGlass or QuestaLint/CDC.

Familiarity with Synthesis tools like Genus or Fusion Compiler.

Working knowledge of SystemVerilog and the RTL front-end flow — able to read violations, assess severity, and disposition findings.

Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles.

Experience building and maintaining CI/CD pipelines (Jenkins, GitLab CI, or GitHub Actions).

Authorization to work in the United States or Canada; visa sponsorship may be considered for exceptional candidates.

On-site Monday through Friday at our Bay Area, Vancouver, or Toronto office.

PREFERRED QUALIFICATIONS

Experience building waiver management systems, violation databases, or design quality dashboards.
Experience with register map automation and IP packaging standards (PeakRDL, SystemRDL, or IP-XACT).
Knowledge of UPF and power intent.
Knowledge of Static Timing Analysis.
Practical experience with LLM APIs or agent frameworks (e.g., Anthropic Claude, OpenAI) applied in a production or team-facing context.
Hands-on experience integrating and releasing digital IP — hierarchy assembly, connectivity closure, versioned collateral, and handoff to internal or external consumers.
Exposure to PHY, SerDes, die-to-die interconnect, or chiplet-based SoC design.
Open-source contributions to design automation, hardware verification, or developer tooling.

About the Company

Eliyan

D2D/C2C interconnect IP licensing

Eliyan provides high-performance interconnect IP and chiplets for chiplet-based systems, including NuLink PHY for die-to-die and chip-to-chip connections and NuGear memory/I O chips, plus a Universal Memory Interface. Its NuLink uses simultaneous bidirectional signaling on a single wire to achieve high bandwidth while staying compatible with standards like UCIe and BoW and using standard organic substrates. The company licenses its IP to chip makers rather than selling completed hardware, focusing on reducing cost, simplifying supply chains, and boosting system-level performance for data centers, AI accelerators, and HPC workloads. Eliyan aims to enable scalable, flexible multi-die designs that can connect to different memory types (HBM, GDDR, DDR) across future process nodes.

Company size: 51-200
Company stage: Series C
Total funding: $295M
Headquarters: Santa Clara, CA
Founded: 2021

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