SoC Power Spec Engineer

Summary

Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for crafting state-of-the-art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs and applications, including AI/ML and power modeling at the SOC/system level for Apple products. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power-efficiency. You will collaborate across many teams including architecture, SOC design, and system design. The job also involves partnering with the lab and silicon characterization/validation teams on correlating the models to the silicon data.

Minimum Qualifications

A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.

Preferred Qualifications

We would prefer our SoC Power Spec Engineer to have the following qualifications: MSEE preferred Deep knowledge of SOC architecture and power modeling. Deep understanding of SOC building blocks including CPU, GPU, caches, memory and media IPs Skills in scripting and data analysis. Understanding of VLSI design flow and CMOS technology and background in EE. Ability to understand and model thermal control loops and throttling mechanisms. Strong teammate with excellent communication skills.

Description

The job involves collaborating across many fields and playing a role of getting innovative products to millions of customers. You will have the opportunity to build new insights into silicon optimization, as well as work with architects, silicon design engineers, software developers, and be involved in silicon/model correlation efforts of mobile SoC design. Your main responsibilities will be: -Modeling power dissipation at the SOC level, including Neural Engines, CPUs, Graphics, compute ( AI/ML) accelerators, media IPs, caches and fabric. -Modeling power dissipation for customer use-cases. -Interacting with the System designers, Technology team, Silicon Validation, and Product Engineering teams to define power targets at the SOC level, and the power delivery. -Working with the power lab and test teams to correlate models to silicon data.