Director of ASIC Design Verification

SambaNova's SN50 RDU for AI at Hot Chips 2026. August 25, 2026 For as new as the dedicated AI accelerator field is, SambaNova is one of the older and more established hardware vendors. The company is now in the fifth generation of their reconfigurable dataflow unit (RDU) technology, with the SN50 that was launched earlier this year. As with the other major AI vendors at this year's Hot Chips conference, the company has come to present new technical details on SN50, and outline what makes it competitive in the burgeoning field of dedicated AI accelerators. SambaNova's hardware has taken on an increased prominence in the industry thanks to the company's connection to Intel. While Intel itself is still trying to catch up on AI accelerators, the company has become increasingly attached to the hip to SambaNova, whose RDUs provide the dedicated, high-efficiency and low-latency AI accelerators that round out Intel's hardware stack. Thus the company's progress with the SN50 (and future RDUs) is material not just for SambaNova, but for Intel as well. Setting the stage, agentic inference is all the rage right now. Where does all the execution time go? SambaNova has a breakdown of it. Most time is spent in decode, especially on DeepSeek V3 where it's 97% of the time, versus 3% for prefill. And decode, in turn, is bandwidth-bound. The FLOPS-per-byte ratio is quite low, even for large batch sizes. Bandwidth utilization is often misunderstood. SambaNova is laying out what they mean for this talk. In short, they aren't talking about just how much HBM bandwidth is being used, but rather the Model Bandwidth Utilization (MBU) model. And specifically, what fraction of that is being used to cache data and otherwise handle data usage. Looking at the current state of tech, GPUs offer low bandwidth usage, even with highly optimized GPU-friendly benchmarks. Things get worse for GPUs when you scale up the number of them; performance does go up, but MBU drops significantly. Meanwhile frontier models require being able to scale up. Again with a GPU example, a GPU can get to around 30TB/second of model bandwidth. But they can't get past that. Enter SambaNova's SN50 dataflow RBU. They have doubled-down on what worked well from SN40, such as the large on-chip SRAM. 5x as many FLOPS as SN40, and it is designed to scale-up to a much larger domain of 256+ chips. And there is a separate scale-out network using 400Gb networking. Notably, there are no I/O dies or similar here. Instead it is just two max reticle dies for the logic, and then HBM stacks for the memory. Though it is interesting that SambaNova's choice of HBM here is quite dated; SN50 still uses HBM2e here (which is going to be a problem in the future as production of the memory is already ramping down). Moving up to the SN50 rack architecture, there are 16 RDUs in a single air-cooled rack, split over two nodes. Diving a bit deeper into SN50 and the dataflow architecture. The core element of the SN50 is the sea of compute cores (PCUs) and memory cores (PMUs). There is no hardware memory management; this is all software managed. Every unit operates when it has input and sends it to the outputs. To better illustrate how the dataflow architecture works, here is an example of how it maps to a transformer. Here is what a GPU looks like. And how it look on the SN50. For compute, data from the HBM is fed into the AGCU portal that control off-chip access, and from there into the PCUs and PMUs. The SRAM amount used is not a function of the size of the model. That was one RDU. How do things scale up for multiple RDUs? SambaNova employs both scale-up and scale-out networking. The Scale-up network is based on 800GbE, while scale-out is 400GbE. And then there is a front-end network. SambaNova uses an all-to-all topology for an 8 socket configuration. To go above 8 sockets, then the scale-up network is employed using Ethernet switches. Links are ganged, and every node is connected to each of two switches in this 64 chip socket configuration. Then things can be scaled out further, in this case employing both scale-up and out for a 512 socket configuration. The key to performance on SN50 is overlap. SN50 supports all forms of model parallelism, and the collective communication forms that these models are built on. Here is a brief look at performance with GEMM benchmarking. The utilization is consistently 70% or higher even at 32 sockets. If you are able to overlap, you can do the compute and communications in parallel. That kind of overlap is not something GPUs can do. The building block for SambaNova is collective communication, which is the purple boxes in these diagrams. And the SRAMs can stream from one to another without having to go through a higher layer (e.g. HBM). Here's a look at parallelism with tensor parallel. Here is a look at the bandwidth utilization that SN has achieved with DeepSeek. Meanwhile they can also use expert parallel (EP) as an additional form of parallelism. This relies on broadcast-dispatch as well as all-to-all dispatch-combine. With all-to-all, one way is to dynamically send everything to the target RDUs. Alternatively, you can just blast everything to all of the RDUs and then filter out things afterwards. The all-to-all method requires a group-by operation at the end of the router to collect (group) the tokens before transmitting them SRAM-to-SRAM. All-to-all also means allowing dynamic traffic. Now here's the other method of broadcast + filter. That is still an SRAM-to-SRAM operation, but with a filter operation on the PCUs of the receiving RDU. This keeps the network traffic parallel; though it does increase it a bit. And by not depending on the router, the transfer can be started early. Here is another DeepSeek example, with SambaNova getting close to 80% bandwidth utilization for loading the experts in MoE. As a result of this, SN50 achieves a high MBU value even at scale, with MBU holding at 45% even with 256 SN50s. And this makes it possible to keep adding RDUs to scale up things even further. This, in turn, means that models don't have to give up bandwidth. Going back to SambaNova's original chart about power scaling, here is what SN50 clusters of different sizes look like. A 512 RDU configuration is able to scale up to an aggregate model bandwidth capacity of over 350 TB/second. The systems can strongly scale, with MBUs still in the 40% range at 512 sockets. Ultimately SambaNova is promoting a very similar picture as other dedicated inference chip firms, using one type of chips for prefill (and midfill), while using separate accelerators (i.e. SN50) for decode. Specifically, they've been using NVIDIA H200 + SN50, with RoCE for transferring between them. Finally, taking a look at that performance in action, based on an Artificial Analysis benchmark of SN50. The hardware achieves over 750 tokens-per-second in MiniMax M2.7.

Callosum raises $100M led by Atomico in one of Europe's largest seed rounds. August 20, 2026 * Having raised $10.25 million in a pre-seed round in February, Callosum has now obtained $100 million in seed funding. * Atomico led the seed round, with Plural, DCVC, and the UK's Sovereign AI Fund also joining. * According to the fund's website, the investment in Callosum was its first, made in April. Callosum, a London-based startup, has raised a $100 million seed round, one of the largest ever in Europe, led by Atomico. This follows its pre-seed round at a $10.25 million valuation led by Plural in February. UK's £500 million Sovereign AI Fund, along with some other unnamed investors and angels, took part. Since its foundation in 2025, Callosum has now raised approximately $110 million in funding. The company has not shared its valuation. From neuroscience PhDs to a nine-figure seed. Callosum was founded by Danyal Akarca and Jascha Achterberg, who first began working together while pursuing their PhDs at Cambridge in neuroscience, computing, and AI. Their research has appeared in Nature journals, and both have held positions at Intel and Google DeepMind. Callosum's method is based on the founders' academic backgrounds. They hold the view that, just as intelligence in nature arises from a variety of neurons, AI should not rely on identical chips. Instead, their software breaks down AI tasks into separate steps and sends each one to the most suitable model and chip rather than using the same hardware for all purposes. As a growing share of industry spending shifts from training to inference, AI companies frequently spend half or more of their revenue on inference. For instance, one step in an autonomous computing task may require fast pattern matching, while another may call for deeper reasoning. The company's system therefore allocates each step to different hardware, thus preventing competition for resources. It claims that its solution is twice as accurate, seven times faster, and four times cheaper for complex tasks compared with using uniform hardware, even though it has not made the technical benchmark figures available. Nvidia's CUDA ecosystem, with its ~85% share of the GPU market, remains Callosum's principal competitor. Cerebras, the wafer-scale chipmaker that went public in May 2026 at a valuation of nearly $56 billion, has now entered into a partnership with Callosum. Although Etched and SambaNova are also developing their own custom chips to improve inference efficiency, their methods are less extensive than Callosum's chip-agnostic approach. A 10x increase in funding since February. The company's new funding will enable it to become a "global heterogeneous integrator" and establish new computing partnerships. Its key partnership with Cerebras focuses on achieving low-latency inference at scale, and it is also entering into a collaboration with the Korean chipmaker Rebellions. "By integrating Cerebras into Callosum's platform, we're making ultra-low-latency inference available exactly where it creates the greatest impact, enabling customers to build AI systems that simply weren't practical before," said Andrew Feldman, Cerebras' chief executive. Sunghyun Park, chief executive of Rebellions, framed the deal as a structural stand against single-vendor lock-in: "Working with Callosum puts our architecture into systems alongside hardware chosen for different parts of the workload, instead of asking one chip to do every job. That's the difference between a partnership and a deployment that only works in one environment or geography." Kanishka Narayan, the UK's minister for artificial intelligence, tied the investment to national chip strategy: "AI is nothing without the chips that underpin it, and the eye-watering demand for them is only going to grow. In the race to develop and use AI, success will depend not just on having access to those chips, but on using them as efficiently as possible." Nvidia believes the total AI infrastructure market could reach at least $1 trillion by 2027, driven primarily by inference workloads. Callosum maintains that no single chip can meet this demand. The UK government has again supported this view since April, even if it has not stated so outright.