Physical Design & Signoff CAD Engineer

Meta's Silicon Engineering team is building custom silicon infrastructure to power the next generation of AI and data center workloads at scale. The Infra Silicon Physical Design CAD team develops and scales the RTL-to-GDSII implementation and signoff flows that our designers use to tape out large, high-performance SoCs on leading-edge process nodes. As an ASIC Engineer for a Physical Design & Signoff CAD Engineer you will own and advance our implementation and signoff methodology from synthesis, place and route, and PPA optimization through timing, physical, and reliability signoff; to build the infrastructure and AI-assisted automation that makes these flows fast, reproducible, and scalable across many designs and teams.