Tesla

Makes electric cars, robotaxis and grid batteries

ASIC RTL Design Engineer - Interconnect & Memory Systems

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNo salary listed

About the Job

Requirements

A degree in Electrical Engineering or Computer Science, or equivalent experience.
At least 3 years of hands-on RTL design experience in SoC interconnect, memory systems, or data path components for custom ASICs.
Strong proficiency in Verilog or SystemVerilog for complex digital design.
A solid understanding of the AXI protocol and high-performance design techniques, such as pipelining and clock domain crossing.
Experience with synthesis, timing analysis, and linting tools, such as Synopsys Design Compiler and SpyGlass.
A proven track record in Network on Chip design, including topology selection, routing algorithms, and Quality of Service mechanisms.
Deep expertise in DMA engine design, memory controller architectures such as DDR/LPDDR interfaces, Memory Management Units, and priority arbiters for multi-master systems.
Experience with high-performance SoC data path optimization for AI/ML accelerators or high-performance computing applications.
Familiarity with verification methodologies such as UVM and scripting languages such as Python or Perl for automation.

Responsibilities

Architect, design, and implement RTL using Verilog or SystemVerilog for high-performance interconnect and memory subsystems, including Network on Chip topologies, DMA controllers, and AXI-based data paths optimized for AI workloads.
Develop and document microarchitecture specifications for memory controllers, Memory Management Units, and arbiters to enable low-latency, high-bandwidth data movement across SoC components.
Define system-level functional requirements for SoC data paths, focusing on throughput, scalability, and integration with compute accelerators.
Perform design analysis, including timing closure, power optimization, and area efficiency, for high-performance memory and interconnect blocks.
Collaborate with cross-functional teams to integrate interconnect intellectual property into full-chip designs, debug issues, and support silicon bring-up and validation.
Contribute to performance modeling and simulation of data path elements to meet hardware performance metrics.
Monitor industry trends in high-performance ASIC design and propose innovations to improve interconnect and memory efficiency.

Category	Tesla SI
Location	Palo Alto, California
Requisition ID	258190
Type	Full-time

Job Description

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in SI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. The Tesla SI Hardware team is looking for an ASIC RTL Design Engineer specializing in interconnect and memory systems to drive the development of next-generation SI accelerators. In this role, you will focus on the critical data path elements of custom ASICs, including Network on Chip (NoC) architectures, DMA engines, memory controllers, Memory Management Units (MMUs), arbiters, and AXI protocol implementations. You will collaborate closely with system architects, verification engineers, physical design teams, and software/firmware developers to deliver high-performance, power-efficient designs that enable massive-scale SI training and inference. This position is based in Palo Alto, CA, or Austin, TX and offers the opportunity to work on cutting-edge hardware that powers Tesla's autonomous driving and SI initiatives.

Job Responsibilities

Architect, design, and implement RTL (Verilog/SystemVerilog) for high-performance interconnect and memory subsystems, including NoC topologies, DMA controllers, and AXI-based data paths optimized for SI workloads
Develop and document microarchitecture specifications for memory controllers, MMUs, and arbiters to ensure low-latency, high-bandwidth data movement across SoC components
Define system-level functional requirements for SoC data paths, focusing on throughput, scalability, and integration with compute accelerators
Perform design analysis, including timing closure, power optimization, and area efficiency, for high-performance memory and interconnect blocks
Collaborate with cross-functional teams to integrate interconnect IP into full-chip designs, debug issues, and support silicon bring-up and validation
Contribute to performance modeling and simulation of data path elements to meet aggressive SI hardware metrics
Stay abreast of industry trends in high-performance ASIC design and propose innovations for interconnect and memory efficiency

Job Requirements

Degree in Electrical Engineering, Computer Science, or equivalent experience
3+ years of hands-on RTL design experience in SoC interconnect, memory systems, or data path components for custom ASICs
Strong proficiency in Verilog or SystemVerilog for complex digital design
Solid understanding of AXI protocol and high-performance design techniques (e.g., pipelining, clock domain crossing)
Experience with synthesis, timing analysis, and linting tools (e.g., Synopsys Design Compiler, SpyGlass)
Ability to work in a fast-paced, collaborative environment with strong problem-solving skills
Proven track record in Network on Chip (NoC) design, including topology selection, routing algorithms, and QoS mechanisms
Deep expertise in DMA engine design, memory controller architectures (e.g., DDR/LPDDR interfaces), MMUs, and priority arbiters for multi-master systems
Experience with high-performance SoC data path optimization for AI/ML accelerators or HPC applications
Familiarity with verification methodologies (e.g., UVM) and scripting (Python/Perl) for automation

About the Company

Tesla

Makes electric cars, robotaxis and grid batteries

Tesla makes electric cars and batteries that store power for homes and utilities, and it develops self-driving software and humanoid robots. In 2023, its Model Y became the first electric vehicle to rank as the world's best-selling car. Buyers order the Model 3 sedan, Model Y SUV, or Cybertruck pickup directly from Tesla instead of through dealers, and they charge on its Supercharger fast-charging network. It also sells Megapack and Powerwall batteries, runs a robotaxi service, and charges drivers a monthly fee for self-driving software that still needs their supervision. Tesla was founded in 2003, with Elon Musk as its lead early investor and a recognized co-founder, and it is based in Austin, Texas.

Company size: 10,001+
Company stage: IPO
Headquarters: Austin, TX
Founded: 2003

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