Cadence Design Systems

Develops EDA software, IP, verification tools

Design Engineering Intern

Silicon & ASIC DesignConfirmed live in the last 24 hours

InternshipShanghai, ChinaNo salary listedIn-person

About the Job

Requirements

A master's degree or higher in microelectronics or electronic engineering.
Strong problem-analysis and teamwork abilities.
Strong spoken and written communication in both Chinese and English.
Familiarity with digital backend tools.
Availability to work at least three days per week for a six- to eight-month internship.

Responsibilities

Implement physical design for high-speed digital DDR and HBM/UCIe/PCIe/eUSB IPs and develop scripts or tools to enhance the current physical-design flow.
Complete project tasks, resolve design issues, and provide flows to check for and prevent similar issues.
Analyze and summarize PPA optimization methodologies and results, and implement optimal design parameters and flows for different projects.
Perform chip physical design, backend place-and-route, static timing analysis, and physical verification.
Collaborate with the team on circuit backend design and delivery, and control design quality and schedule.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the team:
Our team deliver many high-performance products based on the industry’s advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Focus on high speed digital DDR and HBM/UCIe/PCIe/eUSB IPs physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

实习 - 数字后端工程师 (工作地点：上海)

职位描述：
(1)芯片物理设计, 后端布局布线，STA，物理验证等。
(2)团队合作，负责电路后端设计及交付，设计质量和进度控制

职位需求：
(1)微电子,电子工程硕士以上学历
(2)较强的问题分析以及团队合作能力
(3)较强的中英文口语沟通及写作能力
(4)熟悉数字后端工具
(5)积极主动, 有责任心

**每周可以工作至少3天，实习期6-8个月

We’re doing work that matters. Help us solve what others can’t.

About the Company

Cadence Design Systems

Develops EDA software, IP, verification tools

Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company size: 10,001+
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1988

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