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Eliyan

D2D/C2C interconnect IP licensing

Staff AMS CAD Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSan Francisco, CA, USANo salary listed

About the Job

Requirements

  • A Master's degree in electrical engineering, Electronics, or a related field is required.
  • A minimum of 5 years of relevant experience in AMS CAD/design environment support is required.
  • Hands-on experience with industry-standard EDA tools such as Cadence Virtuoso Layout/Schematic, ADE Assembler, Pegasus, Quantus, Calibre, and related tools is required.
  • Strong programming and scripting abilities in Python, Cadence SKILL, Cadence PCELLS, and Shell scripting (Bash/Tcsh) are required.

Responsibilities

  • Download, install, and configure Process Design Kits (PDKs) for analog/mixed-signal design environments.
  • Manage the acquisition and integration of third-party and in-house IP blocks into the design environment.
  • Administer EDA tool installation, upgrades, and license server management to ensure uninterrupted access for design teams.
  • Handle project and workarea setup, including directory structures, access controls, and design environment configuration.
  • Configure and validate simulation model files, including SPICE and statistical models, for accurate circuit simulation.
  • Set up and maintain the Slurm workload manager for efficient job scheduling and compute resource allocation.
  • Establish and maintain Physical Verification flows, including FILL, DRC, LVS, PERC, and Antenna checks.
  • Configure parasitic RC extraction flows for accurate post-layout simulation and analysis.
  • Implement and maintain the Voltus-Fi based Electromigration and IR drop (EMIR) analysis flow.
  • Configure and deploy the EMX electromagnetic simulation flow for passive component and interconnect modeling.
  • Define and maintain the analog macro release procedure for digital hand-off, including GDS, LEF, LIB/DB, CDL, and behavioral models, ensuring completeness, quality checks, and seamless integration into the digital design flow.
  • Work with EDA vendors, including Cadence, Synopsys, and Siemens/Mentor, to evaluate new tools and updates, report bugs, obtain patches, resolve tool-related issues, and drive enhancements aligned with design team requirements.
  • Troubleshoot and resolve issues associated with AMS tools, flows, and design environment configurations.

About the Company

Eliyan

D2D/C2C interconnect IP licensing

Eliyan provides high-performance interconnect IP and chiplets for chiplet-based systems, including NuLink PHY for die-to-die and chip-to-chip connections and NuGear memory/I O chips, plus a Universal Memory Interface. Its NuLink uses simultaneous bidirectional signaling on a single wire to achieve high bandwidth while staying compatible with standards like UCIe and BoW and using standard organic substrates. The company licenses its IP to chip makers rather than selling completed hardware, focusing on reducing cost, simplifying supply chains, and boosting system-level performance for data centers, AI accelerators, and HPC workloads. Eliyan aims to enable scalable, flexible multi-die designs that can connect to different memory types (HBM, GDDR, DDR) across future process nodes.

Company size
51-200
Company stage
Series C
Total funding
$295M
Headquarters
Santa Clara, CA
Founded
2021

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