Gate-level Noise - Signal Integrity, Static Timing Analysis CAD Engineer

Summary

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.

Minimum Qualifications

BS in Electrical Engineering, Computer Engineering, or related technical discipline and 10+ years of industry experience.

Preferred Qualifications

Hands-on experience with signal integrity analysis tools: Tempus, PrimeTime-SI, ETS/Celtic, or equivalent Solid understanding of STA fundamentals and PrimeTime specifics (Tcl coding, attributes, commands, reports) Strong Perl, Tcl, and/or Python scripting skills and a systematic debugging approach Working knowledge of crosstalk, OCV effects, margins, constraints, aggressor selection, and correlation basics BS or MS in a technical discipline Ability to plan and execute tool/methodology evaluations, qualifying a new tool or tool version in a systematic, repeatable manner Exposure to transistor-level analysis and SPICE simulation Expertise in AI/ML-driven and agentic-workflow innovation for CAD and noise/timing flows (LLM-based triage, debug-copilot workflows, agent-based report mining) Experience wrapping existing Perl/Tcl flow scripts as callable tools within an agent framework for natural-language-driven flow operations Familiarity with noise and timing ECO techniques and implementation Excellent communication and presentation skills; ability to coordinate initiatives with design teams and CAD groups with little to no oversight

Description

In this highly visible role, your primary responsibilities will include: Define and architect consistent noise and STA analysis methodology, margins, and tool/version qualification strategy, and drive deployment across multiple projects with minimal oversight comprehensive EM/SEB/thermal methodologies and drive deployment across multiple advanced node designs with minimal oversight Own and drive flows and scripts for core gate-level noise and static timing analysis tools end to end, from constraint setup through sign-off, including automation, quality metrics, and continuous improvement Conduct deep root-cause analysis of noise violations and timing-path anomalies, increasingly accelerated with LLM-agent pipelines that auto-triage and classify failures by severity, aggressor pattern, or known failure signature Serve as the technical authority and primary point of contact for design and Physical Design teams on noise/timing constraint, flow, and closure issues, surfacing best practices Drive noise and STA methodology improvements, using AI coding agents (e.g., Claude Code, Copilot) to rapidly prototype and harden new analysis methodologies, margin models, and waiver-justification logic Build infrastructure for large-scale noise/timing report mining, QoR extraction, and visualization, including agent- or retrieval-backed natural-language query over report corpora Develop and support noise and timing ECO methodology and custom scripts for project tapeout Apply agentic diffing and summarization to accelerate tool and version qualification and flag regressions, while retaining human-in-the-loop judgment on signoff decisions and waivers Create documentation, guidelines, and specs, structured to also serve as grounding context for internal AI assistants supporting the team Mentor junior engineers on noise/STA analysis techniques and best practices